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Table of Contents

Table of Contents

Overview

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Refer to https://

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wiki.trenz-electronic.de/

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display/PD/TE0712+TRM for

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online version of this manual and the rest of available documentation.

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Trenz Electronic TE0712 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, a 10/100 Mbit Ethernet transceiver, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.
Block Diagram
Image Removed
Main Components
Image Removed   Image Removed
...
Programmable oscillator @25 MHz, SiTime SiT8008, U9
...
Programmable quad clock generator, Silicon Labs Si5338, U2
...
10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5
Key Features
  • Xilinx Artix-7 FPGA (15T to 200T) supported by the free Xilinx Vivado WebPACK software
  • Both industrial and commercial temperature ranges available
  • Rugged for high shock resistance and high vibration
  • 1 GByte DDR3 32-bit SDRAM
  • 10/100 Mbit Ethernet PHY
    • MAC address EEPROM
...
  • 32 MByte QSPI Flash memory 
...
4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15
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System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
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4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19
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Serial EEPROM, Microchip 11AA02E48, U7
...
  • (with XiP support)
  • Programmable clock generator
    • Transceiver clock (default 125 MHz)
    • Fabric clock (default 200 MHz)
  • Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
  • 158 FPGA I/Os (78 differential pairs) available via board-to-board connectors (quantity depends on assembly variant)
  • 4 GTP (high-performance transceiver) lanes
    • GTP (high-performance transceiver) clock input
  • On-board high-efficiency DC-DC converters
    • 12A x 1.0V power rail  
    • 1.5A x 1.8V power rail 
    • 1.5A x 1.5V power rail 
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • User configurable LEDs
  • Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Image Added
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Main Components
   Image AddedImage Added
  1. Programmable oscillator @25 MHz, SiTime SiT8008, U9
  2. Programmable quad clock generator, Silicon Labs Si5338, U2
  3. 10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5
  4. Xilinx Artix-7 FPGA XC7A series, U1
  5. 32 MByte QSPI Flash memory, Cypress S25FL256S, U4
  6. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15
  7. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3
  8. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19
  9. Serial EEPROM, Microchip 11AA02E48, U7
  10. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  11. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  12. Samtec Razor Beam™ LSHM-150 B2B connector, JM3
  13. 12A Enpirion EN63A0QI PowerSoC DC-DC converter, U14
  14. Green LED (SYSLED1), D1
  15. Red LED (SYSLED2), D2
Key Features
  • Xilinx Artix-7 (15T to 200T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK software
  • Both industrial and commercial temperature ranges available
  • Rugged for high shock resistance and high vibration
  • 1 GByte DDR3 32-bit SDRAM
  • 10/100 Mbit Ethernet PHY
    • MAC address EEPROM
  • 32 MByte QSPI Flash memory (with XiP support)
  • Programmable clock generator
    • Transceiver clock (default 125 MHz)
    • Fabric clock (default 200 MHz)
  • Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
  • 158 FPGA I/Os (78 differential pairs) available on board-to-board connectors
  • 4 GTP (high-performance transceiver) lanes
    • GTP (high-performance transceiver) clock input
  • On-board high-efficiency DC-DC converters
    • 12A x 1.0V power rail  
    • 1.5A x 1.8V power rail 
    • 1.5A x 1.5V power rail 
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • User configurable LEDs
  • Evenly-spread supply pins for good signal integrity
...
Initial Delivery State
Programmable unit
Content
Notes
Xilinx Artix-7 FPGANot programmedU1
System Controller CPLDProgrammedU3
SPI Flash OTP areaEmptyU4
SPI Flash main array
EmptyU4
SPI Flash Quad Enable bitSetU4
Microchip 11AA02E48
Globally unique EUI-48 (Ethernet MAC address)
U7
Programmable quad clock generator, Silicon Labs Si5338Programmed, CLK1A - 50M, CLK2 - 125M, CLK3 - 50MU2
Signals, Interfaces and Pins
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FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM110VCCIO13Supplied by the baseboard. Not available on XC7A35T assembly variant.
13JM320VCCIO13Supplied by the baseboard. Not available on XC7A35T assembly variant.
14JM183.3V
 

14JM2183.3V
 

14JM343.3V
 

15JM248VCCIO15Supplied by the baseboard.
15JM22VCCIO15Supplied by the baseboard.
16JM148VCCIO16Supplied by the baseboard.
Please refer to the Pin-out  tables page for additional information. 
...
JTAG access to the Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B connector JM2.
JTAG Signal
B2B Pin
TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99
JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC CPLD:
JTAGENJTAG Access To
LowArtix-7 FPGA
HighSystem Controller CPLD
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System Controller I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
Pin NameModeFunctionDefault Configuration
PGOOD
Output
INOUTPower goodActive low when EN1 is low or module power is invalid 
.
otherwhise high impedance
JTAGENInputJTAG selectLow for normal operation, high for System Controller CPLD access.
EN1InputPower EnableWhen forced low, pulls POR_B low to emulate power on reset.
NOSEQ-No functionNot used.
MODE-No functionNot used.
Pin usages depends on Purpose of this IOs depends in the CPLD Firmware, please check also CPLD Firmware description, see: TE0712 CPLD
On-board LEDs
The TE0712 module has 2 LEDs which are connected to the System Controller CPLD. Once FPGA configuration has completed these can be used by the user's design. 
LEDColorSC SignalSC PinNotes
D1GreenSYSLED19Exact function is defined by SC depends on System Controller CPLD firmware.
D2RedSYSLED28Exact function is defined by SC depends on System Controller CPLD firmware.
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Clocking
Si5338 programmable clock generator is used to generate different clocks with 25 MHz oscillator connected to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B connector JM3 (CLKIN2).
The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock must remain at 50 MHz). An I2C I2C bus is connected between the FPGA (master) and clock generator (slave). Proper logic needs to be created in the FPGA to exercise the I2C I2C bus with the correct data. See the reference design section for more information.

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 CLK Output
FPGA Bank
FPGA Pin
IO Standard
Net Name
Default Frequency
NotesCLK0*34
REV 01, REV 02Default Frequency
REV 03 and higher		Notes
CLK035K4/J4DIFF_SSTL15CLK0_P/NOff
--
100MHz LVDS18
NB! Since PCB REV02.
CLK1A--
 

CLK50M50 MHz
50MHz CMOS33
PHY chip RMII reference clock.
CLK1B
*
34R4
 

CLK50M2
CLK50M2
Off
--
50MHz CMOS33
NB! Since PCB REV02.
CLK2216F6/E6AutoMGT_CLK0_P/N125 MHz
125MHz LVDS18
GTP transceiver clock.
CLK335H4/G4DIFF_SSTL15PLL_CLK_P/N50 MHz
 
* See notes.
50MHz LVDS18

Certain B2B connector pins are connected to the FPGA pins which are capable of handling clocking signals from the user’s PCB (baseboard). See schematics B2B page for additional information.
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The 10/100 Mbps Ethernet PHY TLK106 (U5) by Texas Instruments is connected to the FPGA bank 14 using Reduced Media Independent Interface standard (RMII). The RMII standard has reduced set of data lines (two rather than four) and a higher clock frequency (50 MHz rather than 25 MHz) compared to the Media Independent Interface standard (MII). A management interface is also available allowing access to registers in the PHY chip. Transmit and receive signals are connected to the B2B connector JM1. The magnetics and RJ-45 jack must be placed on the user's PCB (baseboard).
FPGA Ethernet Signals

 
FPGA PinSignal NameSignal Description
N17ETH-RSTEthernet reset, active-low.
N15LINK_LEDEthernet LED pin indication mode: in mode 1 - LINK, in mode 2 - ACT.
R16MDC
Ethernet management clock.
P17MDIOEthernet management data.
P14ETH_TX_D0Ethernet transmit data 0. Output to Ethernet PHY.
P15ETH_TX_D1Ethernet transmit data 1. Output to Ethernet PHY.
R14ETH_TX_ENEthernet transmit enable.
N13ETH_RX_D0Ethernet receive data 0. Input from Ethernet PHY. 
N14ETH_RX_D1Ethernet receive data 0. Input from Ethernet PHY. 
P20ETH_RX_DVEthernet receive data valid.
All signals are connected to the FPGA bank 14 and correspond to LVCMOS33 standard.
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TE0712-02 module can also be powered by split 5V/3.3V power sources if preferred. In such case apply 5V to B2B connectors VIN pins and 3.3V to 3.3VIN pins, although lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 5V/3.3V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises).
Power-On Sequence
For the highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0712 module.
Power Rails
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Power Rail Name
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B2B Connector JM1 Pin
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B2B Connector JM2 Pin
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Direction
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VIN
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1.8V
...
Module internal 1.8V level. Maximum 300mA available.
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High-Range bank supply voltage (from the baseboard).
...
when VIN/VOUT ratio rises).
Power-On Sequence
For the highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0712 module.
 Info
3.3Vout or 1.8Vout from the module  can be used to enable  power supply for variable bank power and periphery, see also
4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs
FAQ#PCBDesign  → Power sequencing for variable IO banks and connected periphery


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Power Rails
Power Rail Name
B2B Connector JM1 Pin
B2B Connector JM2 Pin
Direction
Notes
VIN
1, 3, 52, 4, 6, 8InputSoM supply voltage (from the baseboard).
3.3VIN13, 15-InputSoM supply voltage (from the baseboard).
1.5V-19OutputModule internal 1.5V level.
1.8V
39-Output
Module internal 1.8V level. Maximum 300mA available.
3.3V -10, 12OutputModule internal 3.3V level.
3.3V14
OutputModule internal 3.3V level. Not on all 4x5 modules
VCCIO13-1, 3Input
High-Range bank supply voltage (from the baseboard).
VCCIO15-7, 9InputHigh-Range bank supply voltage (from the baseboard).
VCCIO169, 11-InputHigh-Range bank supply voltage (from the baseboard).
VREF_JTAG-91OutputJTAG reference voltage (3.3V).
Board to Board Connectors
 Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors
Technical Specifications
Absolute Maximum Ratings
Parameter
MinMax
Units
Reference Document
VIN supply voltage
-0.36.5
V
EP53F8QI datasheet.
3.3VIN supply voltage-0.36.0VTPS748 datasheet.
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage-0.4 VCCO + 0.55VXilinx datasheet DS181
GTP transceivers Tx/Rx input voltage-0.51.26VXilinx datasheet DS181
Storage temperature
-55
100
°C
See IM4G16D3EABG datasheet.
Recommended Operating Conditions
ParameterMinMaxUnitsReference Document
VIN supply voltage2.45.5VEP53F8QI datasheet.
3.3VIN supply voltage2.95.5VTPS748 datasheet.
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage-0.20VCCO + 0.2VXilinx datasheet DS181

Physical Dimensions
  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
 Image Added   Image Added
Weight
16 - 27 g,  Plain module (depends on variant).
8.8 g,  Set of nuts and bolts.
Currently Offered Variants 
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hiddentrue
idComments
Set correct link to the shop page overview table of the product on English and German.
Example for TE0706:
    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706
    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

 Scroll Title
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titleTrenz Electronic Shop Overview
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sortDirectionASC
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cellHighlightingtrue
Trenz shop TE0712 overview page
English pageGerman page

Revision History
Hardware Revision History
DateRevision
Notes
PCNDocumentation Link
2016-12-0902Second production revisionClick to see PCNTE0712-02
2013-12-02
01
First production revision

TE0712-01
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Image Added
Document Change History
Date
Revision
Contributors
Description
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modified-date
modified-date
dateFormatyyyy-MM-dd
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infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse


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infoTypeModified by
typeFlat
showVersionsfalse
Updated Download link for this document
2022-12-22
v.31
Waldemar Hanemann 
  • Variants will changed to shop search
2020-07-03v.23John  Hartfiel
  • add power sequencing notes
2019-01-10v.22John  Hartfiel
  • Update document change history
  • Update system controller and power sequencing chapter
2017-12-15v.18John  Hartfiel
  • Update Board to Board (B2B) I/Os
2017-12-12v.15John  Hartfiel
  • Replace B2B connector section
  • Typo correction on Clocking section
2017-05-29v.13Jan Kumann
  • Variants table added.
  • Key Features section relocated.
2017-03-01v.7
Board to Board Connectors
...
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Reference Document
...
VIN supply voltage
...
V
...
Storage temperature (ambient)
...
-55
...
100
...
°C
...
Recommended Operating Conditions
...
 Note
Assembly variants for higher storage temperature range are available on request.
Physical Dimensions
  • Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
  • Mating height with standard connectors: 8mm
  • PCB thickness: 1.6mm
  • Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
 Image Removed   Image Removed
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Weight
21 g Plain module.
8.8 g Set of nuts and bolts.
Revision History
Hardware Revision History
...
Notes
...
01
...
First production revision
...
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Image Removed
Document Change History
Date
Revision
Contributors
Description
2017-03-01
John Hartfiel
  • BUGFIX in the description of System Controller 
 IO section2017-03-01v3.1John Hartfiel
  • I/O section
  • Update Clocking Section
2017-01-26
V3 
v.3
Jan Kumann
  • New block diagram.
  • Few corrections.
2017-01-20
V2
v.2

Jan Kumann
  • Revised version.
2013-12-02 
V0
v.1Antti Lukats
  • Work in progress.
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