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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
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Table of contents
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Overview
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General Design description
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MicroBlaze Design with HyperRAM memory test example.
This reference designs is bundled with a FREE evaluation edition of the commercially proven, low-cost, low-circuit area, high performance, HyperBus Memory Controller (HBMC) IP supplied by Synaptic Laboratories Ltd. Synaptic Labs HBMC IP is commercially proven in both Intel and Xilinx projects, and was selected by Intel. This FREE HBMC IP evaluation license never expires, and no customer registration or NIC ID is required.
You can check for and obtain the latest version of the FREE evaluation HBMC IP from S/Labs website for Xilinx on S/Labs HBMC IP (Free Trail IP) . Please send your HBMC IP support questions to info@synaptic-labs.com
Key Features
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Excerpt |
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Revision History
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- 2018.2 update
- new HBMC IP version (v1_3_57)
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- initial release
Release Notes and Know Issues
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Requirements
Software
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Hardware
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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Design supports following carriers:
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Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Additional Sources
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Prebuilt
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<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
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File
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File-Extension
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Description
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Basic Design Steps
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
- Copy Application (memory_tests.elf) into \firmware\microblaze_0\
- Regenerate Design:
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado - (alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash_mcsfile
Note: Alternative use SDK or setup Flash on Vivado manually - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Open Vivado HW Manager
- Program Bitfile
Usage
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HBMC IP is a 10 minute run-time limited evaluation version of the full-edition |
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Power On PCB (Do not restart, if you use Bitfile programming)
Note: FPGA Loads Bitfile from Flash
UART
- Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Uart Console:
Xilinx Memory test on HyperRAM
System Design - Vivado
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Block Design
Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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Design specific constrain
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set_property PACKAGE_PIN A13 [get_ports HB_CLK0_0]
set_property PACKAGE_PIN A14 [get_ports HB_CLK0n_0]
set_property PACKAGE_PIN E17 [get_ports {HB_dq_0[0]}]
set_property PACKAGE_PIN B17 [get_ports {HB_dq_0[1]}]
set_property PACKAGE_PIN F18 [get_ports {HB_dq_0[2]}]
set_property PACKAGE_PIN F16 [get_ports {HB_dq_0[3]}]
set_property PACKAGE_PIN G17 [get_ports {HB_dq_0[4]}]
set_property PACKAGE_PIN D18 [get_ports {HB_dq_0[5]}]
set_property PACKAGE_PIN B18 [get_ports {HB_dq_0[6]}]
set_property PACKAGE_PIN A16 [get_ports {HB_dq_0[7]}]
set_property PACKAGE_PIN E18 [get_ports HB_RWDS_0]
set_property PACKAGE_PIN D17 [get_ports HB_CS1n_0]
set_property PACKAGE_PIN J17 [get_ports HB_RSTn_0]
#set_property PACKAGE_PIN A18 [get_ports HB_CS0n_0 ]
#set_property PACKAGE_PIN J18 [get_ports HB_INTn_0 ]
#set_property PACKAGE_PIN C17 [get_ports HB_RSTOn_0]
#
# FPGA Pin Voltage assignment
#
set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0_0]
set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0n_0]
set_property IOSTANDARD LVCMOS18 [get_ports {HB_dq_0[*]}]
set_property IOSTANDARD LVCMOS18 [get_ports HB_CS1n_0]
set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTn_0]
set_property IOSTANDARD LVCMOS18 [get_ports HB_RWDS_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_CS0n_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_INTn_0]
#set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTOn_0]
#set_property PULLUP true [get_ports HB_RSTOn_0]
#set_property PULLUP true [get_ports HB_INTn_0]
#
#Hyperbus Clock - change according to clk pin on PLL
#
create_generated_clock -name clk_0 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]
create_generated_clock -name clk_90 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT1]
create_generated_clock -name clk_180 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT2]
#
#100Mhz clock freqeuncy - change accordingly
#
set hbus_freq_ns 10
set dqs_in_min_dly -0.5
set dqs_in_max_dly 0.5
set HB_dq_ports [get_ports HB_dq_0[*]]
#
#Create RDS clock and RDS virtual clock
#
create_clock -period $hbus_freq_ns -name rwds_clk [get_ports HB_RWDS_0]
create_clock -period $hbus_freq_ns -name virt_rwds_clk
#
#Input Delay Constraint - HB_RWDS-HB_DQ
#
set_input_delay -clock [get_clocks virt_rwds_clk] -max ${dqs_in_max_dly} ${HB_dq_ports}
set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -max ${dqs_in_max_dly} ${HB_dq_ports} -add_delay
set_input_delay -clock [get_clocks virt_rwds_clk] -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay
set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay
set_multicycle_path -setup -end -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] 0
set_multicycle_path -setup -end -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] 0
set_false_path -fall_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -setup
set_false_path -rise_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -setup
set_false_path -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -hold
set_false_path -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -hold
set_false_path -from [get_clocks clk_0] -to [get_clocks rwds_clk]
set_false_path -from [get_clocks rwds_clk] -to [get_clocks clk_0]
#
#Output Delay Constraint - HB_CLK0-HB_DQ
#
create_generated_clock -name HB_CLK0_0 -source [get_pins */*/*/U_IO/U_CLK0/dq_idx_[0].ODDR_inst/C] -multiply_by 1 -invert [get_ports HB_CLK0_0]
set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports}
set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports}
set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} -clock_fall -add_delay
set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} -clock_fall -add_delay
set_false_path -from [get_pins */*/*/U_HBC/*/dq_io_tri_reg/C] -to ${HB_dq_ports}
set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_1_reg/CLR]
set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_2_reg/CLR]
set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_3_reg/CLR]
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Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
memory_tests
Xilinx default memory test.
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- 2018.2 release
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- Documentation update
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- 2017.4 release
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