Page History

Overview

Online version of this manual and other related documents can be found at Refer to https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0712 for downloadable version of this manual and the rest of available documentation.

Trenz Electronic TE0712 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, a 10/100 Mbit Ethernet transceiver, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages.

...

Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

Image Added

Main Components

Image Added   Image Added

1. Programmable oscillator @25 MHz, SiTime SiT8008, U9

2. Programmable quad clock generator, Silicon Labs Si5338, U2

3. 10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5

4. Xilinx Artix-7 FPGA XC7A series, U1

5. 32 MByte QSPI Flash memory, Cypress S25FL256S, U4

6. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15

7. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3

8. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19

9. Serial EEPROM, Microchip 11AA02E48, U7

10. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
11. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
12. Samtec Razor Beam™ LSHM-150 B2B connector, JM3
13. 12A Enpirion EN63A0QI PowerSoC DC-DC converter, U14
14. Green LED (SYSLED1), D1
15. Red LED (SYSLED2), D2

Key Features

• Xilinx Artix-7 (15T to 200T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK software
• Both industrial and commercial temperature ranges available
• Rugged for high shock resistance and high vibration
• 1 GByte DDR3 32-bit SDRAM
  
• 10/100 Mbit Ethernet PHY
  • MAC address EEPROM
• 32 MByte QSPI Flash memory (with XiP support)
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
    
  • Fabric clock (default 200 MHz)
    
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 158 FPGA I/Os (78 differential pairs) available on board-to-board connectors
• 4 GTP (high-performance transceiver) lanes
  • GTP (high-performance transceiver) clock input
• On-board high-efficiency DC-DC converters
  • 12A x 1.0V power rail  
  • 1.5A x 1.8V power rail 
  • 1.5A x 1.5V power rail 
• System management and power sequencing
• eFUSE bit-stream encryption
• AES bit-stream encryption
• User configurable LEDs
• Evenly-spread supply pins for good signal integrity

Block diagram

Put you block diagram here...

Main components

Put top and bottom pics with labels of the real PCB here...

Add description list of PCB labels here...

Key features

List key features here, like FPGA type, amount and type of RAM, type of flash, etc.

...

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Signals, Interfaces and Pins

Board to Board (B2B) I/

...

Os

FPGA bank number and number of I/O signals connected to the SoC's I/O bank and B2B connector: 

For detailed information about the pin out, please refer to the Pinout Tables. 

Default MIO Mapping

...

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

...

USB Interface

USB PHY is provided with ...

...

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

...

Please refer to the Pin-out  tables page for additional information.

JTAG Interface

JTAG access to the ... Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B connector ..JM2.. 

...

JTAGEN pin in B2B connector

...

JM1 is used to select JTAG access for FPGA or SC CPLD:

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Boot Modes

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

...

MODE Signal State

...

high or open

...

SD Card

...

low or ground

...

QSPI

LED's

...

Onboard Peripherals

Processing System (PS) Peripherals

...

Clocking

...

PS CLK

...

33.3333 Mhz

...

...

PS_CLK

...

PS subsystem main clock.

...

GT REFCLK1

...

125 Mhz

...

...

Default clock is 125 MHz.

LEDs

The TE0712 module has 2 LEDs which are connected to the System Controller CPLD. Once FPGA configuration has completed these can be used by the user's design. 

Clocking

Si5338 programmable clock generator is used to generate different clocks with 25 MHz oscillator connected to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B connector JM3 (CLKIN2).

The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock must remain at 50 MHz). An I2C bus is connected between the FPGA (master) and clock generator (slave). Proper logic needs to be created in the FPGA to exercise the I2C bus with the correct data. See the reference design section for more information.

Image Added

Board Connector Clock Inputs

Certain B2B connector pins are connected to the FPGA pins which are capable of handling clocking signals from the user’s PCB (baseboard). See schematics B2B page for additional information.

On-board Peripherals

32 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL256S (U14) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

System Controller CPLD

System Controller CPLD (Lattice MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.

DDR3 SDRAM

The TE0712-02 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.

• Part number: IM4G16D3EABG-125I
• Supply voltage: 1.5V
• Organization: 32M words x 16 bits x 8 banks
• Memory speed: limited by Xilinx Artix-7 speed grade and MIG

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet PHY

The 10/100 Mbps Ethernet PHY TLK106 (U5) by Texas Instruments is connected to the FPGA bank 14 using Reduced Media Independent Interface standard (RMII). The RMII standard has reduced set of data lines (two rather than four) and a higher clock frequency (50 MHz rather than 25 MHz) compared to the Media Independent Interface standard (MII). A management interface is also available allowing access to registers in the PHY chip. Transmit and receive signals are connected to the B2B connector JM1. The magnetics and RJ-45 jack must be placed on the user's PCB (baseboard).

FPGA Ethernet Signals

MAC Address SEEPROM

TE0712-02 module has a 2 Kbit Serial Electrically Erasable PROM (SEEPROM, U7).  It provides pre-programmed 48-bit Extended Unique Identifier (EUI-48™) to identify network hardware MAC address which is write-protected to ensure tamper-proof designs. This SEEPROM can be accessed by UNI/O^® serial interface bus using Manchester encoding techniques. The clock and data are combined into a single, serial bit stream (SCIO), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. The bus is controlled by a master device (Xilinx Artix-7) which determines the clock period, controls the bus access and initiates all operations, while the SEEPROM works as a slave. Refer to Microchip's 11AA02E48 datasheet for more information.

Power and Power-On Sequence

Power Supply

Single 3.3V power supply (for both VIN and 3.3VIN power rails) with minimum current capability of 3A

RTC - Real Time Clock

An temperature compensated  ... is used for Real Time Clock ...

PLL - Phase-Locked Loop

There is a I2C programmable clock generator ... chip on the ...

PLL connection

...

MAC-Address EEPROM

A ... EEPROM (U..) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification.

Power and Power-On Sequece

Power Supply

Power supply with minimum current capability of ...A for system startup is recommended.

Power Consumption

...

Typical module power consumption is between 2-3W. Exact power consumption is to be determined.

TE0712-02 module can also be powered by split 5V/3.3V power sources if preferred. In such case apply 5V to B2B connectors VIN pins and 3.3V to 3.3VIN pins, although lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 5V/3.3V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises) * TBD - To Be Determined soon with reference design setup.

Power-On Sequence

For the highest efficiency of the on-board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3..

Power Rails

...

Voltages on B2B-

Connectors

...

B2B

...

B2B

...

B2B

...

Input/

Output

...

Bank Voltages

...

Bank          

...

Voltage

...

TE0715-xx-15        

...

TE0715-xx-30           

...

3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS181 - "Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics" for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0712 module.

Power Rails

Board to Board Connectors

Board to Board Connectors

... put some B2B related information here if you have them ...

Please take care, B2B connectors are of interest when on module. B2B on baseboard has no meaning for the user of the baseboard.

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

• Module size: ... 50 mm × ... 40 mm.  Please download the assembly diagram for exact numbers.
• Mating height with standard connectors: ... mm.8mm
• PCB thickness: 1... mm.6mm
• Highest part on PCB: approx. 2... mm5mm. Please download the step model for exact numbers.

 All dimensions are given shown in mmmillimeters. Put mechanical drawings here...

 Image Added   Image Added

Operating Temperature Ranges

...

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

... 21 g - Plain .module..

8... 8 g - Set of nuts and bolts and nuts.

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Image AddedPut pic of PCB silk screen here showing model and revision ...

Document Change History

Disclaimer