Page History

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Trenz Electronic TE0712 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, a 10/100 Mbit Ethernet transceiver, 1 GByte of DDR3 SDRAM, 32 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Block Diagram

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Main Components

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Programmable oscillator @25 MHz, SiTime SiT8008, U9

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Programmable quad clock generator, Silicon Labs Si5338, U2

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10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5

Key Features

• Xilinx Artix-7 FPGA

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32 MByte QSPI Flash memory, Cypress S25FL256S, U4

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4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15

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System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3

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4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19

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Serial EEPROM, Microchip 11AA02E48, U7

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• (15T to 200T) supported by the free Xilinx Vivado WebPACK software
• Both industrial and commercial temperature ranges available
• Rugged for high shock resistance and high vibration
• 1 GByte DDR3 32-bit SDRAM
  
• 10/100 Mbit Ethernet PHY
  • MAC address EEPROM
• 32 MByte QSPI Flash memory (with XiP support)
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
    
  • Fabric clock (default 200 MHz)
    
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 158 FPGA I/Os (78 differential pairs) available via board-to-board connectors
• 4 GTP (high-performance transceiver) lanes
  • GTP (high-performance transceiver) clock input
• On-board high-efficiency DC-DC converters
  • 12A x 1.0V power rail  
  • 1.5A x 1.8V power rail 
  • 1.5A x 1.5V power rail 
• System management and power sequencing
• eFUSE bit-stream encryption
• AES bit-stream encryption
• User configurable LEDs
• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

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1. Programmable oscillator @25 MHz, SiTime SiT8008, U9

2. Programmable quad clock generator, Silicon Labs Si5338, U2

3. 10/100 Mbps Ethernet PHY transceiver, Texas Instruments TLK106, U5

4. Xilinx Artix-7 FPGA XC7A series, U1

5. 32 MByte QSPI Flash memory, Cypress S25FL256S, U4

6. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U15

7. System Controller CPLD, Lattice Semiconductor MachXO2-256HC, U3

8. 4 Gbit DDR3 SDRAM, Intelligent Memory IM4G16D3EABG, U19

9. Serial EEPROM, Microchip 11AA02E48, U7

10. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
11. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
12. Samtec Razor Beam™ LSHM-150 B2B connector, JM3
13. 12A Enpirion EN63A0QI PowerSoC DC-DC converter, U14
14. Green LED (SYSLED1), D1
15. Red LED (SYSLED2), D2

Key Features

• Xilinx Artix-7 (15T to 200T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK software
• Both industrial and commercial temperature ranges available
• Rugged for high shock resistance and high vibration
• 1 GByte DDR3 32-bit SDRAM
  
• 10/100 Mbit Ethernet PHY
  • MAC address EEPROM
• 32 MByte QSPI Flash memory (with XiP support)
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
    
  • Fabric clock (default 200 MHz)
    
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 158 FPGA I/Os (78 differential pairs) available on board-to-board connectors
• 4 GTP (high-performance transceiver) lanes
  • GTP (high-performance transceiver) clock input
• On-board high-efficiency DC-DC converters
  • 12A x 1.0V power rail  
  • 1.5A x 1.8V power rail 
  • 1.5A x 1.5V power rail 
• System management and power sequencing
• eFUSE bit-stream encryption
• AES bit-stream encryption
• User configurable LEDs
• Evenly-spread supply pins for good signal integrity

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Initial Delivery State

Signals, Interfaces and Pins

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Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin usages depends on CPLD Firmware, see: TE0712 CPLD

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Clocking

Si5338 programmable clock generator is used to generate different clocks with 25 MHz oscillator connected to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B connector JM3 (CLKIN2).

The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock must remain at 50 MHz). An I2C I²C bus is connected between the FPGA (master) and clock generator (slave). Proper logic needs to be created in the FPGA to exercise the I2C I²C bus with the correct data. See the reference design section for more information.

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Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

21 16 - 27 g,  Plain module (depends on variant).

8.8 g,  Set of nuts and bolts.

Revision History

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V3

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