Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0710+TRM for online version of this manual and the rest of available documentation.

Trenz Electronic TE0710 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, two 10/100 Mbit Ethernet PHYs, 512 MByte DDR3 SDRAM, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.

Key Features

• Industrial-grade Xilinx Artix-7 FPGA (15T to 100T) , supported by the free Xilinx Vivado WebPACK development tool

• Rugged for shock and high vibration

• 512 MByte DDR3 SDRAM

• Dual 10/100 Mbit Ethernet PHY

  • MAC Address EEPROM

• 32 MByte QSPI Flash memory (with XiP support)

• 100 MHz MEMS oscillator

• Plug-on module with 2 × 100-pin high-speed hermaphroditic strips

• 112 FPGA I/Os (51 differential pairs) are available via board-to-board connectors

• On-board high-efficiency DC-DC converters

  • 4.0 A x 1.0 V power rail

  • 1.0 A x 1.8 V power rail

  • 1.0 A x 1.5 V power rail

• System management and power sequencing

• eFUSE bit-stream encryption

• AES bit-stream encryption

• User LED

• Evenly-spread supply pins for good signal integrity

NB! Assembly options for cost or performance optimization are available upon request.

Block Diagram

Figure 1: TE0710-02 block diagram.

Main Components

Figure 2: TE0710-02 PCB.

1. Xilinx Artix-7 FPGA , U5
2. Voltage regulator for DDR3 SDRAM (Texas Instruments TPS51206), U2
3. 512 MByte DDR3 SDRAM (Memphis MEM4G08D3EABG), U12
4. 1A PowerSoC DC-DC converter for 1.5V (Altera EN5311QI), U10
5. 32 MByte Quad SPI Flash memory (Cypress S25FL256S), U7
6. System Controller CPLD (Lattice Semiconductor LCMXO2-256HC), U4
7. 4A PowerSoC DC-DC converter for 1.0V (Altera EN6347QI), U1
8. Programmable oscillator @25.000000 MHz for Ethernet reference clock (SiTime SiT8008), U9
9. B2B connector (0,40 mm Razor Beam™ High Speed Hermaphroditic Strip LSHM-150), JM2
10. B2B connector (0,40 mm Razor Beam™ High Speed Hermaphroditic Strip LSHM-150), JM1
11. 1A PowerSoC DC-DC converter for 1.5V for 1.8V (Altera EN5311QI), U11
12. 10/100 Mbps Ethernet PHY (Texas Instruments TLK106), U3
    
13. 10/100 Mbps Ethernet PHY (Texas Instruments TLK106), U6
    
14. 2 Kbit serial EEPROM with UNI/O serial interface (Microchip 11AA02E48T-I/TT), U13
    
15. Programmable oscillator @100.000000 MHz for reference clock (SiTime SiT8008), U8
    

Initial Delivery State

Table 1: TE0710-02 module initial delivery state.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGAs I/O banks, voltages and B2B connections:

Table 2: FPGA I/O banks.

Please refer to Pin-out tables page for more information.

JTAG Interface

JTAG access to the Xilinx Artix-7 and System Controller CPLD is provided through B2B connector JM2.

Table 3: JTAG interface connector.

System Controller I/O Pins

Special purpose pins are connected to the System Controller CPLD which have following default function:

Table 4: Special purpose pins description of the System Controller CPLD.

On-board LEDs

There are three LEDs available on TE0710-02 SoM. Two are status LEDs, and one can be freely used by user design. The user LED is routed to the FPGA as 'USERLED'.

When the FPGA is not configured the status LEDs will flash continuously. Once the FPGA configuration has completed, the status LEDs can be used by the user FPGA design.

Table 5: On-board LEDs.

Clocking

The TE0710-02 SoM is equipped with two MEMS oscillators to provide clock signals for two on-board Ethernet PHYs and DDR3 SDRAM.

Table 6: Clocks overview.

On-board Peripherals

32 MByte Quad SPI Flash Memory

An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

System Controller CPLD

System Controller CPLD (Lattice MachXO2-256HC, U4) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters are not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.

DDR3 SDRAM

The TE0710-02 SoM has one 512 MByte volatile DDR3 SDRAM IC (U12) for storing user code and data.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2A for system startup is recommended.

Table 7: Typical power consumption during normal operation.

Lowest power consumption is achieved when powering the module from single 3.3V power supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For highest efficiency of on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS181 (for Artix7) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0710-02 module.

A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stable. Than 3.3V supply will be available on the B2B connector pins.

The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are as follows:

• Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
• Apply 3.3V to pins VIN and 3.3VIN on the board connectors.

Power Rails and Bank Voltages

Table 8: Power rails on B2B connectors.

Table 9: FPGA bank voltages.

See Xilinx Artix-7 datasheet DS181 for allowed voltage ranges.

Board to Board Connectors

Variants Currently In Production

Table 10: Differences between TE0710-02 variants.

Technical Specifications

Absolute Maximum Ratings

Table 11: Absolute maximum ratings.

Recommended Operating Conditions

Table 12: Recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact Trenz Electronic for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.
• Mating height with standard connectors: 8mm
• PCB thickness: 1.4mm+/-10%
• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

Figure 3: Physical dimensions of the TE0710-02 SoM.

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

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