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Refer to http://trenz.org/teg2000-info for the current online version of this manual and other available documentation.
This page describes briefly how to generate the fpga configuration file (Bitstream/cfg file) from the blink-example and how to program the FPGA. For a more detailed description of the tools follow the Quick start section of colognechip ug1002.
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Design supports following modules:
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Design supports following carriers:
*used as reference |
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Reference Design is available on:
It contains the tools, the example project blink and several other sample projects(those are not documented here).
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The design source files exist in verilog and in vhdl.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity blink is port ( clk : in std_logic; rst : in std_logic; led : out std_logic ); end entity; architecture rtl of blink is component CC_PLL is generic ( REF_CLK : string; -- reference input in MHz OUT_CLK : string; -- pll output frequency in MHz PERF_MD : string; -- LOWPOWER, ECONOMY, SPEED LOW_JITTER : integer; -- 0: disable, 1: enable low jitter mode CI_FILTER_CONST : integer; -- optional CI filter constant CP_FILTER_CONST : integer -- optional CP filter constant ); port ( CLK_REF : in std_logic; USR_CLK_REF : in std_logic; CLK_FEEDBACK : in std_logic; USR_LOCKED_STDY_RST : in std_logic; USR_PLL_LOCKED_STDY : out std_logic; USR_PLL_LOCKED : out std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK_REF_OUT : out std_logic ); end component; signal clk0 : std_logic; signal counter : unsigned(26 downto 0); begin socket_pll : CC_PLL generic map ( REF_CLK => "10.0", OUT_CLK => "100.0", PERF_MD => "ECONOMY", LOW_JITTER => 1, CI_FILTER_CONST => 2, CP_FILTER_CONST => 4 ) port map ( CLK_REF => clk, USR_CLK_REF => '0', CLK_FEEDBACK => '0', USR_LOCKED_STDY_RST => '0', USR_PLL_LOCKED_STDY => open, USR_PLL_LOCKED => open, CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK_REF_OUT => open ); process(clk0) begin if rising_edge(clk0) then if rst = '0' then counter <= (others => '0'); else counter <= counter + 1; end if; end if; end process; led <= counter(26); end architecture; |
## blink.ccf # # Date: 2022-10-21 # # Format: # <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>; # # Additional constraints can be appended using the pipe symbol. # Files are read line by line. Text after the hash symbol is ignored. # # Available pin directions: # # Pin_in # defines an input pin # Pin_out # defines an output pin # Pin_inout # defines a bidirectional pin # # Available pin constraints: # # SCHMITT_TRIGGER={true,false} # enables or disables schmitt trigger (hysteresis) option # PULLUP={true,false} # enables or disables I/O pullup resistor of nominal 50kOhm # PULLDOWN={true,false} # enables or disables I/O pulldown resistor of nominal 50kOhm # KEEPER={true,false} # enables or disables I/O keeper option # SLEW={slow,fast} # sets slew rate to slow or fast # DRIVE={3,6,9,12} # sets output drive strength to 3mA..12mA # DELAY_OBF={0..15} # adds an additional delay of n * nominal 50ps to output signal # DELAY_IBF={0..15} # adds an additional delay of n * nominal 50ps to input signal # FF_IBF={true,false} # enables or disables placing of FF in input buffer, if possible # FF_OBF={true,false} # enables or disables placing of FF in output buffer, if possible # LVDS_BOOST={true,false} # enables increased LVDS output current of 6.4mA (default: 3.2mA) # LVDS_TERM={true,false} # enables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only # # Global IO constraints can be set with the default_GPIO statement. It can be # overwritten by individual settings for specific GPIOs, e.g.: # default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten # Pin_in "clk" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; Pin_in "rst" Loc = "IO_EB_B0"; # SW3 Pin_out "led" Loc = "IO_SB_B4"; # D1 |
No additional software is needed.
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