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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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Date | Vivado | Project Built | Authors | Description |
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2018-08-27 | 2017.1 | TE0701_zsys_SDSoC_EDDP_FOC-vivado_2017.1-build_05_20180827095945.zip | UTIA | initial release |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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PetaLinux | 2017.1 | needed |
SDx | 2017.1 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
TE0720-03-2IF | TE0720_2IF | REV03 | 1 GB | 32 | ||
TE0720-03-l1if | TE0720_L1IF | REV03 | 512MB (L) | 32 | ||
TE0720-03-1CF | TE0720_1CF | REV03 | 1 GB | 32 | ||
TE0720-03-2EF | TE0720_2EF | REV03 | 1 GB | 32 | ||
TE0720-03-07S | TE0720_07S | REV03 | 1 GB (L) | 32 |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TE0701-6 |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
TEC0053-04 - EDPS Power Stage | https://shop.trenz-electronic.de/en/TEC0053-04-EDPS-Power-Stage?c=474 |
BLDC Motor with mounted Encoder (1000SI) | https://shop.trenz-electronic.de/en/28170-BLDC-Motor-with-mounted-Encoder-1000SI?c=474 |
Interchangeable Plug with four adapters and cable, 12V/2.5A | https://shop.trenz-electronic.de/en/28169-Interchangeable-Plug-with-four-adapters-and-cable-12V/2.5A?c=35 |
2x Pmod Cable Kit: 12-pin | https://shop.trenz-electronic.de/en/26742-Pmod-Cable-Kit-12-pin?c=37 |
Pmod Cable Kit: 6 pin cable connector kit, 30 cm (12") in length | https://shop.trenz-electronic.de/en/25250-Pmod-Cable-Kit-6-pin-cable-connector-kit-30-cm-12-in-length?c=37 |
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For general structure and of the reference design, see Project Delivery - AMD devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
SDSoC | <design name>/../SDSoC_PFM | SDSoC Platform will be generated by TE Scripts |
Type | Location | Notes |
---|---|---|
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
TE0701_zsys_SDSoC_EDDP_FOC 2017.1 platform with TEC0053 Power Stage
3-phase brush-less DC motor control with field oriented control (FOC) algorithm implemented in SDSoC 2017.1 on TE0720 module and TE0701-06 carrier board. The TEC0053-04 - EDPS Power Stage controls the BLDC Motor with mounted Encoder.
The following steps are describing how to connect and setup hardware parts shown in the Figure above.
Set TE0701-06 carrier board FMC_VADJ = 3.3V by switch S4:
S4 | Setup |
---|---|
S4_1 | ON |
S4_2 | ON |
S4_3 | ON |
S4_4 | OFF |
Set FMC_VADJ (set in step 1 to 3.3V) to drive both, the VIOTA and VIOTB by this arrangement of J16, J17 and J21.
Jumper | Configuration |
---|---|
J6 | Short 1-2 |
J17 | no connection |
J21 | Short 2-3 |
VIOTA will provide 3.3V to PMOD J5 and FMC_VADJ will provide 3.3V to PMOD J6
Set switch S3 of the TE0701-06 carrier board to:
S3 | Setup |
---|---|
S3_1 | any |
S3_2 | any |
S3_3 | ON |
S3_4 | OFF |
S3_1 and S3_2 serve as general purpose pins connected to the CPLD on the TE0701-06.
Before connecting to TEC0053-04 by PMOD 12pin cables, power on the TE0701-06 (12V) and measure presence of the 3.3V voltage on the TE0701-06 PMOD J5 pin 12 and pin 6 and on the TE0701-06 PMOD J6 pin 12 and pin 6. |
Connect TEC0053 to two 3.3V PMOD connectors on TE0701 carrier with two
Pmod 12-pin cables as shown in following image.
Motor rotation encoder is connected to the TEC0053-04 - EDPS Power Stage Pmod 6 pin cable connector kit. See the orientation and position of the 5 wire connection. There are 6 pins on the TEC0053-04 board. There are only 5 pins on the motor encoder. Pin 1 connects to pin 1. 6-th wire is unconnected on the motor encoder side.
3-phase of the motor phases are connected to the TEC0053-04 - EDPS Power Stage points A, B and C:
A: green wire; B: red wire; C: black wire.
# First PMOD cable 12-pin: # Connections of # TE0701-06 J5 with TEC0053 J9 set_property PACKAGE_PIN W18 [get_ports {SDV}]; #TE0701-06 J5:7 with TEC0053 J9:7 set_property PACKAGE_PIN W17 [get_ports {ENC_A}]; #TE0701-06 J5:8 with TEC0053 J9:8 set_property PACKAGE_PIN Y19 [get_ports {ENC_B}]; #TE0701-06 J5:9 with TEC0053 J9:9 set_property PACKAGE_PIN AA19 [get_ports {ENC_I}]; #TE0701-06 J5:10 with TEC0053 J9:10 # GND #TE0701-06 J5:11 with TEC0053 J9:11 # 3,3V #TE0701-06 J5:12 with TEC0053 J9:12 set_property PACKAGE_PIN Y16 [get_ports {SCLK}]; #TE0701-06 J5:1 with TEC0053 J9:1 set_property PACKAGE_PIN W16 [get_ports {SDI1}]; #TE0701-06 J5:2 with TEC0053 J9:2 set_property PACKAGE_PIN Y18 [get_ports {SDI2}]; #TE0701-06 J5:3 with TEC0053 J9:3 set_property PACKAGE_PIN AA18 [get_ports {SDI3}]; #TE0701-06 J5:4 with TEC0053 J9:4 #GND #TE0701-06 J5:5 with TEC0053 J9:5 #3,3V #TE0701-06 J5:6 with TEC0053 J9:6 #All signals connected by the first PMOD cable cable belong to TE0720 Zynq Bank 33. # Second PMOD cable 12-pin: # Connections of #TE0701-06 J6 with TEC0053 J8 set_property PACKAGE_PIN Y8 [get_ports {GL[0]}]; #TE0701-06 J6:7 with TEC0053 J8:7 set_property PACKAGE_PIN Y9 [get_ports {GL[1]}]; #TE0701-06 J6:8 with TEC0053 J8:8 set_property PACKAGE_PIN V9 [get_ports {GL[2]}]; #TE0701-06 J6:9 with TEC0053 J8:9 #GND #TE0701-06 J6:11 with TEC0053 J8:11 #3,3V #TE0701-06 J6:12 with TEC0053 J8:12 set_property PACKAGE_PIN AA7 [get_ports {GH[0]}]; #TE0701-06 J6:1 with TEC0053 J8:1 set_property PACKAGE_PIN AA6 [get_ports {GH[1]}]; #TE0701-06 J6:2 with TEC0053 J8:2 set_property PACKAGE_PIN U11 [get_ports {GH[2]}]; #TE0701-06 J6:3 with TEC0053 J8:3 #GND #TE0701-06 J6:5 with TEC0053 J8:5 #3,3V #TE0701-06 J6:6 with TEC0053 J8:6 # Second PMOD Cable 12-pin contains these two wires unconnected to the SDSoC design: #set_property PACKAGE_PIN V10 [get_ports {gpio_0_tri_io[0]}]; #TE0701-06 J6:10 - TEC0053 J8:10 #set_property PACKAGE_PIN U12 [get_ports {gpio_0_tri_io[1]}]; #TE0701-06 J6:4 - TEC0053 J8:4 #All signals connected by the second Pmod cable belong to TE0720 Zynq Bank 13. |
The older TE0701-04 or TE0701-05 carrier boards can be used with the identical platform, but |
Unzip Reference Design
Do not change base folder name after extraction! The name must be: |
CD to the directory and run from win terminal:
_create_win_setup.cmd
run from win terminal:
_use_virtual_drive.cmd
reply to select an virtual drive name (example X): X
reply: 0
cd X:\zsys
This is shortest possible path and directory name for building of the platform
in windows (to respect the 260 character limitations.)
Do not change the name of the directory /zsys |
Enable SDSOC, set install path of Xilinx tools, set your hardware assembly option in: "design_basic_settings.cmd" Select one of these supported modules (1,4,5,6,7):
ID | TE Module |
---|---|
1 | te0720-03-2if |
4 | te0720-03-l1if |
5 | te0720-03-1cf |
6 | te0720-03-2ef |
7 | te0720-03-07s |
NOTE: Selection 7 supports the TE0720-03-14S-1C module (xc7z014sclg484-1c device).
TCL-Console type: TE::hw_build_design -export_prebuilt
Find hardware handoff file .hdf under prebuilt folder abd copy it to Ubuntu 16.04, with installed Petalinux 2017.1 SDK.
Before petalinux project can be built, the executable rights must be set for these files: ./init_config.sh |
In Ubuntu 16.04, build Petalinux image image.ub and uboot u-boot.elf using Petalinux BSP provided under "os" folder and place new images to correct subfolder in prebuilt/os
Vivado project will be permanently modified in this step by copying constrain files locally to project.
If needed, recreate original project with batch file (step 4) to restore original Vivado project with externally linked constrains. |
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | Authors | Description |
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v.17 | UTIA |
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2018-08-15 | v.1 |
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