Template Revision 1.8 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD" |
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
Table of contents |
JTAGEN pin is already pulled up to 3.3V for access to Intel MAX 10.
With carrier board TEIB0006: Set DIP Switch S1-1 to OFF position.
For more Information see Firmware description TEI0006 Intel MAX 10 → JTAG.