Table of contents

CPLD Access  

Set B2B Pin JM1-89 (JTAGEN) to VDD (3.3V)

With TE0701:

• not possible on TE0701-01 up to TE0701-06

With TE0703 and TE0703 default CPLD firmware:

1. Connect MiniUSB cable to J4
2. Set DIP Switch S2-2 to OFF and S2-3 to ON position, see TE0703 CPLD - CC703S#CC703S-JTAG
3. Power ON the board
4. Run "Lattice Diamond Programmer"

5. Select "Create new project from JTAG chain" and press "OK"

With TE0705:

1. Connect MiniUSB cable to J7
2. Set DIP Switch S3-ENJTAG, S3-M1 and S3-M2 to ON position, see TE0705 CPLD#JTAG
3. Power ON the board
4. Run "Lattice Diamond Programmer"

5. Select "Create new project from JTAG chain" and press "OK"

With TE0706:

1. Connect MiniUSB cable to XMOD
2. Set DIP Switch S1-2 to OFF position, see TE0706 TRM#4-bitDIP-switch
3. Power ON the board
4. Run "Lattice Diamond Programmer"

5. Select "Create new project from JTAG chain" and press "OK"

Available CPLD Firmware

• TE0823 CPLD - Firmware description with different Variants for PCB REV03 and newer
  • QSPI / SD Boot Modi - Default delivered, QSPI or SD Boot Mode is selectable (Special FSBL for QSPI Programming with Boot Mode /= JTAG will be provided for Vivado 2017.4 Reference Design and newer).
  • QSPI / JTAG Boot Modi - Use QSPI  or JTAG Boot Mode is selectable
  • JTAG / SD Boot Modi - SD or JTAG Boot Mode is selectable 
  • JTAG / QSPI / SD Boot Modi - QSPI, SD or JTAG Boot Mode is selectable (CPLD Pin 23 (NOSEQ) is used as second Boot Mode pin to select JTAG Boot Mode). Attention: This need 7 Series 4x5 Carrier CPLD Firmware update.

Download

• TE0823/<PCB Revision>/Firmware/
  • Use files from the subfolders of your PCB revision

General instructions