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Disclaimer and Notice

This document is work in progress.

 

Prize's and Rewards

The Challenge went public before we had finalized what can be offered as rewards. We are very happy to see that despite it the interest has been pretty high. But lets make the Challenge a bit more Challenging by revealing the prizes.

We did set up 3 categories in the Xilinx Blog announcement. We are adding some more to keep the Challenge even more challengig.

Deadline 3rd of July, send entries to challenge@trenz.biz email.

Category

  1. UltraFast
  2. Ultimate Theory
  3. Maker DIY Hacker
  4. Ultra Short
  5. Alternative

Ultra Short: make up SHORTEST description to describe how the solution works. Time counts, the first one submitting shortest sentence is the winner. I myself did shorten the shortest sentence several times, and no there is no hint how short it finally was.

Alternative: You think you some alternative solution? Describe it!

 

Challenger Prize's

A "FPGA Challenge" PCB Board is the award. Preliminary specification:

  1. FPGA: Xilinx Artix A35T CSG325
  2. On Board Xilinx tools compatible USB JTAG and UART
  3. On Board "noiseless" power supplies - no switching supplies only LDO
  4. Challenge Circuitry - different circuitry that implements the challenge solutions in different ways
  5. Surprise Circuits

We will put onto that PCB as many as feasible different circuits that implement the proposed circuits submitted as the challenge solution. A list of those circuit/solution and prelimary schematic will be added here. Up to 10 such "challenger PCB" will be offered as prize.

 

Grand Prize

If there is a qualifying winner then one Xilinx UltraScale MPSoC Starter KIT with ZU3 device is set as the grand prize. 

 

Challenge Entries

Here some Design Challenge Entries together with Design Analyze Notes. 

 

UltraFast #1

This was the first submission that "passed" the set criteria for "UltraFast" Category. This solution was first submitted as response at HackaDay and later re-submitted with Drawing included as response to Xilinx Blog Entry.

 

 

Design Analyze Notes

This Schematic is best possible solution using only the components given implementing a Zero IF or Low IF Software Defined Radio with Xilinx 7 Series FPGA. This schematic omits components for ADC anti-alias filter and input AC coupling. This circuit will work if the RF input is either externally AC coupled or has DC common mode in Xilinx XADC input mode compliance range. 

 

UltraFast #2

This is really nice solution provided by Harmon Instruments

Design Analyze Notes

This solution is technically the most correct one so far as XADC is set to proper DC Common mode level and input is also AC coupled so there is no requirement for external signal DC level or coupling type. When I first looked at this solution I did not realize that it has different principle of operation that my own solution and UltraFast solution #1.

I have not tested if this circuit really works, I think it does, probably there are problems with very large signals. Also to be noted that the RF signal at FPGA I/O pin will swing below GND potential of 0V!

 

 

UltraFast #3

 

UltraFast #4

Solution from Zygo

Assumptions:

  1. The 4 R and 4 C doesn’t include power distribution and decoupling
  2. “Receiver” means capable of rejecting most or all competing signals not at the desired frequency.
  3. The frequency used as the example is a portion of the ham band that is only used for CW or digital modes. No AM/FM/SSB is required, although capability for newer digital modes such as PSK31 would be nice.

My proposed design includes:

  1. A DDS core as a local oscillator, using the sign bit to provide a square wave at the LO frequency.
  2. Two OBUFs with complementary enables. When enabled, the signal is grounded, when disabled, the signal passes. Alternating the enables at the LO frequency creates a synchronous modulator. Unfortunately, the square wave drive means that there are images at frequencies related to odd harmonics of the LO frequency.
  3. RC LPF for anti-aliasing. Alternately, this could have been done with one C (differential, but some common mode noise rejection concerns), or three C (delta, less concern about matching of the two C). The ±2 mV single-ended signal becomes ±1.4 mV differential after the filter. In any case, that leaves me with one or more C unused.
  4. XADC to digitize the signal. I’m assuming that -1.4 mV is sufficiently small that it will not exceed the common mode limits. The ±1.4 mV signal is only ±12 counts, but we’re not doing music, and we have some digital processing gain, so that should be sufficient.
  5. DFT to demodulate the signal. I normally implement a DFT with a Blackman window on the coefficients to save multiplies. I also add an extra +π in the math so that zero phase of the coefficients is at the center of the data window, not at the first point as seen in all the textbooks.
  6. Optional complex CIC filter of the DFT output for digital modes that have narrow bandwidth.
  7. The complex signal could be used directly, or it could be converted to magnitude/phase with a CORDIC.

Ballpark values:

  • ADC sample rate = 1 MHz
  • RC LPF bandwidth = 250 kHz
  • IF frequency 200 kHz
  • DDS LO frequency = Signal frequency + 200 kHz
  • DFT center frequency = 200 kHz
  • DFT -3 dB BW = 3 kHz
  • DFT size = 1 MHz / 3 kHz = 332 (rounded to even)
  • DFT update rate = 6 kHz
  • DFT overlap = 2x
  • DFT processing gain = sqrt(3/500) = 44 dB

Design Analyze Notes

This is a DC (Direct Conversion) Receiver using Differential Gain switch as the Mixer. I am sure it would work as is. Another C could be used as input AC coupling. There is potential issue with XADC common mode range but that would not prevent functional operation.

As of processing gain and sensitivy figures well there is lots of digital magic that can be done inside the FPGA. Above is XADC input with no signal applied, the input noise spans 6 LSB of the ADC raw value, marked is LSB value of 250 microvolts. Without too much pushing in the signal processing path input signals in order of 100 microvolt can still be received.

 

TDC-ADC Solution #1

On the left side we have the RF-Input, which is AC-coupled to remove any DC contents from our signal. Next to the coupling the signal path splits into two lanes, the upper signal is the "I" data of our SDR. The lower one is shifted by 90 degrees, by the capacitor. Therefore it is our "Q" data. Both are sampled with a TDC based ADC like this. With the TDC based ADC we can archive very high sampling rates, so we can get our "I" and "Q" data with 500Mhz. As we already have "I" and "Q", we do not need to do much more processing in the FPGA, as the data already represents the frequency, the peak amplitude and the envelope. With circuit diagram, you could build a 500 MHz SDR just from the given components.

Design Analyze Notes

  1. This solution depends heavily on TDC based ADC and refers an online document describing that ADC implementation on Xilinx 6 Series FPGA. If we now look a the drawing we see 7 Series. Of course the TDC ADC method can be used on 7 Series as well, but it is in no way limited to 7 Series only. So this is already first hint that this is not the solution for the Challenge.
  2. The 2 Capacitors parallel to the 2 Resistors are not needed, so we have two Capacitors we have no use for?
  3. LVDS signal inputs are set to DC offset 0V and RF signal would appear on those input as signal with swing to both positive as negative. While some signal receiption may be there still the signal would be heavily distorted at least.
  4. SDR with 500 MHz? The TDC based ADC referenced from the challenge entry was presented with 200 MHz ADC data output rate. Pushing the ADC update rate to 500MHz may be possible (is possible).
  5. I/Q Receiver? OK, it would work as is, if we are able to implement the TDC-ADC with 500 MHz data update rate, and if we have the Q channel set to 90 degrees at 500Mhz then we may be able to process this signal. The second channel will virtually double our maximum receive bandwidth. However we would have much better results if we just double the ADC data rate be sampling the same signal with same phase with 2 ADC channels interleaved 180 degrees at ADC Sample rate. Now we have removed from the schematic one more Capacitor and one Resistor as the external phase shifting network is not required.

 

 

 

Solution Path

We all have different knowledge, experience and way of thinking. But we all have some skills to solve "Abstract Problems". Lets take a look how we can apply those "abstract problem solving skills" to this challenge. First we should should absorbe all given information. Then we will "scan" this information to see if we can identify most relevant parts and if there are any visible or hidden hints to the solution. Lets look at the original drawing I posted:

Why is the Frequency range given as LF - 500MHz? LF (Low Frequency) is in no way specified as some specific fixed frequency, the upper end is however set as fixed number. Why? And why 500 MHz? Or even better question could it be as high as 1000 MHz?

Now the last question we can answered immediately: no it can not be as high as 1000 MHz!

Why ? Simple reason, if the design would work at 1000 MHz then the challenge would have set the upper range as 1000 MHz, as it would be so much more cool and challenging! So why 500 and not say 550 or 600? If the design can work at 500 would it work at 501? Most likely yes. At 510? Most likely yes. So why 500? The answer is abvious, it is the largest SAFE frequency value that is most round and cool as a number. Until this point we did analyze a very small part of the challenge without using any knowledge of Xilinx devices.

Lets proceed, we read from left to right: "Xilinx 7 Series". Why does it say "7 Series"? Can we answer this? Or lets ask, would the solution work with previous series (3,5,6) ? I think we can answer this, if the solution would also work on say 6 Series, then the Challenge would not say "7 Series". So from here we can make one conclusion that there must be one special feature that 7 Series has, and all previous generations do not have. And that this feature is REQUIRED for the challenge solution.

When we are at this point we are a lot closer to the solution, we know that if we compare the features of 7 series to other families, we can figure out a "special feature" that our solution must use. Here we unfortunately have to look into the datasheet and product manuals (unless we know them from memory to required depth of details). Lets make a table with feature comparison.

FeatureGeneration 3,5,67 Series
Max Clock> 500MHz> 500Mhz
XADCNoYes
Gigabit TransceiverOptionalOptional

Not so much of knowledge of Xilinx FPGA's and technologies is required to make the above table and not so many documents to read. So with rather little knowledge and small amount of datasheet study we have found a feature that MUST be used. The solution must use XADC. We also can see that the solution should not use Gigabit Transceivers, as they are not present in all 7 Series devices (and the challenge does specify the devices as generic 7 Series).

If we summarize our findings so far then we know that the solution must use XADC and that the upper frequency limit is set by the maximum Clock rate the FPGA can use.

Now we can look the challenge from different view, the solution should be some type of radio receiver. Can we dig deeper here? Yes we can, we could start making a list of known Radio Receiver Types and then try to analyze them one by one to assign some probability to each of them.

This is now interesting - a very quick internet search will not give this list in clear form, so more than one link from google search results has to be checked out to make the list, here it is:

  1. Detector Radio or direct amplifying Receiver
  2. Regen &Co
  3. (Super)Heterodyne &Co
  4. Direct Conversion Receiver
  5. Zero-IF and Low IF Receiver
  6. Direct Sampling (RF Sampling)

Lets see how many we can exclude safely from the list!

The easiest to exclude is Direct Sampling Receiver. Xilinx 7 Series XADC maximum bandwidth is 300 KHz and sampling rate 1 MSPS, this is far too low to directly sample signals at 500 MHz. Even if 500 fold under-sampling would work, the analog path bandwidth is just too low.

What is the next one we can fully exclude? If we look at the classical Heterodyne Receivers (google image search?) then well it is at least hard to imagine that someone can build a super-Heterodyne receiver with 4 resistors and 4 capacitors. I would exclude this type. Now our list has less entries:

  1. Detector Radio or direct amplifying Receiver
  2. Regen &Co
  3. Direct Conversion Receiver
  4. Zero IF and Low IF Receiver

Can you exclude any more types from the above list? I did think Regen type could be excluded, but well I have received one proposed challenge solution that I can not sort to any other type as some very exotic type of Regen (if it works). Still the likelihood that the solution is some regenerative receiver is very low, so we can exclude it from our list for now.

Can we exclude Detector Radio? Well we could make detector radio if we want using the challenge constraints, but the likelihood that this is the real solution to the challenge is very low. 

As you can see there are exactly 4 Resistors and 4 Capacitors needed to implement a Detector Radio with Xilinx 7 Series FPGA. You do not think this would work? You can try to prove that it does not. Until that I claim that I can add net names to the circuit above that will explain how it works.

Still, the Detector Radio was not the Challenge Solution so now we have on our list only two types left:

  1. Direct Conversion Receiver
  2. Zero-IF and Low IF Receiver

What can we say for sure now? Can we exclude one? You are not sure? Can we exclude two? This can be answered - we can not exclude two as we would have nothing left in our list. So one of the two choices must remain as possible solution. Can we say something more? Can we choose the one that can not be excluded? This indeed is possible. If it is not possible to make DC Receiver then we can also not make Zero IF type receiver as the Zero IF is more complex than Direct Conversion Receiver.

Now we are pretty far on the path to the solution, what we have gathered is information that it is possible to build a Direct Conversion Receiver covering a Frequency up to at least to 500 MHz using the following components:

We also know that we need to use XADC. There is something else we can conclude: If the solution is a DC Receiver than the "enhanced solution" could be Zero-IF Receiver?

Now all that is left is to implement it.

 

Links and references

 

 

 

 

 

 

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