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- SMA Connectors, J1,J3,J5,J7,J9,J11
- U.FL (UMCC ) Connectors, J2,J4,J6,J8, J10, J12...16
- Green LEDs, D6...11
- B2B Connector, J18
- B2B Connector, J17
- Micro SD Card Connector, J28
- Reset Push Button, BTN1
- PCIe 6 Pin Connector, J19
- Micro USB2.0 Connectors, J29-J30
- Gigabit RJ45 Connector, J31
- DIP Switch, S1
- UEC5 Connector, J22,J24
- UCC8 Connector, J23,J25
- 4x1 Pin Header, J21
- FTDI, U12
- Green LEDs, D1...3
- 4x1 Pin Header, J20
- EEPROM, U15
- PCIe-8x-kurz Card, J26
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| Page properties |
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- Overview of Boot Mode, Reset, Enables.
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Push Button BTN1 is provided to switch OFF all power supplies on RFSoC board.
| Scroll Title |
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| anchor | Table_OV_BPRST |
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| title | Boot Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE State| Boot Mode | --- | ---- | |
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | I/O | Note |
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RESETN | J17- 36 | Input | Connected to Push Button, BTN1 |
| B2B | I/O | Note |
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RESETN | J17- 36 | Input | Connected to Push Button, BTN1 |
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There is a DIP switch S1 provided for enabling CPLD Enable and I/Os in order to configure the system controller CPLDand set the FPGA boot mode. The DIP Switch setting must should be set like the following table.
| Scroll Title |
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| anchor | Table_OV_DIP |
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| title | CPLD Configuration |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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DIPDefault Note| S1A | On | SCL pin| FPGA boot config | Bit 0, CPLD Firmware dependent. | | S1-B | CPLD_IO1 |
S1BOn | S1COn | | PROGRAMN pin | | S1-D | CPLD_JTAGEN |
S1D | On | JTAGENB
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Boot Mode must be set using DIP Switch S1 on CPLD provided on the module TE0835. Please note that the DIP Switch is active low.
| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | Boot Mode |
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| S1-A | S1-B |
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| JTAG | ON | ON | | QSPI Flash | ON | OFF | | SD Card | OFF | OFF |
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Signals, Interfaces and Pins
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