Page History

Notes :

• list of software which was used to generate the design

Notes :

• list of software which was used to generate the design

Notes :

• content of the zip file

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only

  SI5338_CLK0 Counter: 

  Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

# GT Clocks
#B128-1
set_property PACKAGE_PIN N27 [get_ports {PL_MGT_CLK_clk_p[0]}]
#B129-1
set_property PACKAGE_PIN J27 [get_ports {PL_MGT_CLK_clk_p[1]}]
#B228-1
set_property PACKAGE_PIN J8  [get_ports {PL_MGT_CLK_clk_p[2]}]
#B130-1
set_property PACKAGE_PIN E27 [get_ports {PL_MGT_CLK_clk_p[3]}]
#B229-1
set_property PACKAGE_PIN E8  [get_ports {PL_MGT_CLK_clk_p[4]}]
#B230-1
set_property PACKAGE_PIN B10 [get_ports {PL_MGT_CLK_clk_p[5]}]

## DP
set_property PACKAGE_PIN AB1 [get_ports dp_aux_data_in]
set_property PACKAGE_PIN V9 [get_ports dp_hot_plug_detect]
set_property PACKAGE_PIN AA8 [get_ports dp_aux_data_out]
set_property PACKAGE_PIN AA3  [get_ports dp_aux_data_oe_n]
set_property IOSTANDARD LVCMOS18 [get_ports dp_*]
## LED
set_property PACKAGE_PIN K14 [get_ports {LED[0]}]
set_property PACKAGE_PIN K10 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED*}]

• optional chapter separate

• sections for different apps

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};

/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 1 100000000>;
    maximum-speed = "super-speed";
};
 

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};



/* ETH */

&gem3 {
        phy-handle = <&phy0>;
        phy0: phy0@1 {
                device_type = "ethernet-phy";
                reg = <1>;
        };
};



/* SD1 */

&sdhci1 {
    // disable-wp;
    no-1-8-v;

};


&i2c0 {
    i2cswitch@76 { // I2C Switch U13
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x76>;
        i2c-mux-idle-disconnect;

        i2c@2 { // FMCD (/dev/i2c-3)
            #address-cells = <1>;
            #size-cells = <0>;

#    C10	 FF01_MPRS            reg = <2>;
                 };
        i2c@3 { // FMCE (/dev/i2c-4)
            #address-cells = <1>;

#    C11	 FF00_MPRS            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // FMCB (/dev/i2c-5)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // FMCC (/dev/i2c-6)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // PLL (/dev/i2c-7)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;

            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <78800000>;

            };
        };
    };
    i2cswitch@77 { // I2C Switch U37
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;

        i2c@0 { // SFP2 (/dev/i2c-9)
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // FMCA (/dev/i2c-10)
                                     
#    D11	 FF31_MPRS                                                       
#    D12	 FF30_MPRS                                                       
#    E10	 FF20_MPRS                                                       
#    E11	 FF11_MPRS                                                       
#    E12	 FF21_MPRS                                                       
#    J12	 FFA_SDA                                                         
#    J14	 FFA_SCL                                                         
#    K10	 FFD_MPRS                                                        
#    K11	 FFD_MSEL                                                        
#    K12	 FFC_MPRS                                                        
#    K14	 FFA_INTL                                                        
#    L10	 FFD_INTL                                                        
#    L12	 FFC_MSEL                                                        
#    L13	 FFA_MPRS                                                        
#    L14	 FFA_MSEL                                                        
#    M10	 FFD_SDA                                                         
#    M11	 FFB_SDA                                                         
#    M13	 FFB_SCL                                                         
#    N10	 FFD_SCL                                                         
#    N11	 FF_AB_RSTL                                                      
#    N12	 FF_CD_RSTL                                                      
#    N13	 FFB_MSEL                                                        
#    N14	 FFB_INTL                                                        
#    P12	 FFC_INTL                                                        
#    P13	 FFC_SCL                                                         
#    P14	 FFB_MPRS                                                        
#    R14	 FFC_SDA                                                         
#
#     E3	 PEX_FATAL_ERRORn      REV02 only                                          
#     E4	 PEX_GPIO3             REV02 only                                          
#     E5	 PEX_LANE_GOOD2n       REV02 only                                          
#     F4	 PEX_LANE_GOOD1n       REV02 only                                          
#     F5	 PEX_LANE_GOOD0n       REV02 only                                          
#
#     F6	 DSPLL1_RST_N                                                    
#     F7	 DSPLL0_RST_N                                                    
#
#    G11	 W_DISABLE1n         REV01 other name                                                      
#    G12	 W_DISABLE2n         REV01 other name                                            
#    G13  M2M_SLEEP           REV02 only
#
#    F10	 SSD1_CLKRQ          REV01 only                                            
#    F13	 SSD1_WAKE           REV01 only                                            
#    G10	 SSD1_PERSTn         REV01 only                                            
#    G13	 M2M_SLEEP           REV01 other nameSSD1_SLEEP                                                      
#


set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK23                } [get_ports {BUTTON[0]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AL23                } [get_ports {BUTTON[1]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AJ24                } [get_ports {BUTTON[2]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK24                } [get_ports {BUTTON[3]}]

set_property -dict { IOSTANDARD DIFF_SSTL12_DCI  PACKAGE_PIN G26          } [get_ports {diff_clock_rtl_clk_p}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N24                } [get_ports {ddr4_act_n}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J27                } [get_ports {ddr4_adr[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J24                } [get_ports {ddr4_adr[1]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F27                } [get_ports {ddr4_adr[2]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E26                } [get_ports {ddr4_adr[3]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M25                } [get_ports {ddr4_adr[4]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN D26                } [get_ports {ddr4_adr[5]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K27                } [get_ports {ddr4_adr[6]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E27                } [get_ports {ddr4_adr[7]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K26                } [get_ports {ddr4_adr[8]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H26                } [get_ports {ddr4_adr[9]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L24                } [get_ports {ddr4_adr[10]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F28                } [get_ports {ddr4_adr[11]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J23                } [get_ports {ddr4_adr[12]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J26                } [get_ports {ddr4_adr[13]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L23                } [get_ports {ddr4_adr[14]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K24                } [get_ports {ddr4_adr[15]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H23                } [get_ports {ddr4_adr[16]}]
## /* dummy for ddr4-ram */
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G25                } [get_ports {ddr4_adr17[0]}] 


set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N26                } [get_ports {ddr4_ba[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G23                } [get_ports {ddr4_ba[1]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M23                } [get_ports {ddr4_bg[0]}]
#set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23                } [get_ports {ddr4_bg[1]}]   
## /* dummy for ddr4-ram */
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23                } [get_ports {ddr4_bg1[0]}]   

set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN F25                } [get_ports {ddr4_ck_t[0]}]
set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN E25                } [get_ports {ddr4_ck_c[0]}]

set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L25                } [get_ports {ddr4_cke[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N23                } [get_ports {ddr4_cs_n[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P18                } [get_ports {ddr4_dm_n[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K19                } [get_ports {ddr4_dm_n[1]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D19                } [get_ports {ddr4_dm_n[2]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G22                } [get_ports {ddr4_dm_n[3]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K29                } [get_ports {ddr4_dm_n[4]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E29                } [get_ports {ddr4_dm_n[5]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C36                } [get_ports {ddr4_dm_n[6]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E32                } [get_ports {ddr4_dm_n[7]}]

set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N19                } [get_ports {ddr4_dqs_c[0]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN J22                } [get_ports {ddr4_dqs_c[1]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B21                } [get_ports {ddr4_dqs_c[2]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN E20                } [get_ports {ddr4_dqs_c[3]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F30                } [get_ports {ddr4_dqs_c[4]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A32                } [get_ports {ddr4_dqs_c[5]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A40                } [get_ports {ddr4_dqs_c[6]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C34                } [get_ports {ddr4_dqs_c[7]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N20                } [get_ports {ddr4_dqs_t[0]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN K22                } [get_ports {ddr4_dqs_t[1]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C21                } [get_ports {ddr4_dqs_t[2]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F20                } [get_ports {ddr4_dqs_t[3]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN G30                } [get_ports {ddr4_dqs_t[4]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B31                } [get_ports {ddr4_dqs_t[5]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A39                } [get_ports {ddr4_dqs_t[6]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN D34                } [get_ports {ddr4_dqs_t[7]}]

set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H24                } [get_ports {ddr4_odt[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N25                } [get_ports {ddr4_reset_n}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N21                } [get_ports {ddr4_dq[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M18                } [get_ports {ddr4_dq[1]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M21                } [get_ports {ddr4_dq[2]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M20                } [get_ports {ddr4_dq[3]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P21                } [get_ports {ddr4_dq[4]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L18                } [get_ports {ddr4_dq[5]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M22                } [get_ports {ddr4_dq[6]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L19                } [get_ports {ddr4_dq[7]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H19                } [get_ports {ddr4_dq[8]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L20                } [get_ports {ddr4_dq[9]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H20                } [get_ports {ddr4_dq[10]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K21                } [get_ports {ddr4_dq[11]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G20                } [get_ports {ddr4_dq[12]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K20                } [get_ports {ddr4_dq[13]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H21                } [get_ports {ddr4_dq[14]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J21                } [get_ports {ddr4_dq[15]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B22                } [get_ports {ddr4_dq[16]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C20                } [get_ports {ddr4_dq[17]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A22                } [get_ports {ddr4_dq[18]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A19                } [get_ports {ddr4_dq[19]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B23                } [get_ports {ddr4_dq[20]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B20                } [get_ports {ddr4_dq[21]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A23                } [get_ports {ddr4_dq[22]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A20                } [get_ports {ddr4_dq[23]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F22                } [get_ports {ddr4_dq[24]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E19                } [get_ports {ddr4_dq[25]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E22                } [get_ports {ddr4_dq[26]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D21                } [get_ports {ddr4_dq[27]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F23                } [get_ports {ddr4_dq[28]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F19                } [get_ports {ddr4_dq[29]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D22                } [get_ports {ddr4_dq[30]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E21                } [get_ports {ddr4_dq[31]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F31                } [get_ports {ddr4_dq[32]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J28                } [get_ports {ddr4_dq[33]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J30                } [get_ports {ddr4_dq[34]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H28                } [get_ports {ddr4_dq[35]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F32                } [get_ports {ddr4_dq[36]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G28                } [get_ports {ddr4_dq[37]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H30                } [get_ports {ddr4_dq[38]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F29                } [get_ports {ddr4_dq[39]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E31                } [get_ports {ddr4_dq[40]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C30                } [get_ports {ddr4_dq[41]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C31                } [get_ports {ddr4_dq[42]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B30                } [get_ports {ddr4_dq[43]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D31                } [get_ports {ddr4_dq[44]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C29                } [get_ports {ddr4_dq[45]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A30                } [get_ports {ddr4_dq[46]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A29                } [get_ports {ddr4_dq[47]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C42                } [get_ports {ddr4_dq[48]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B36                } [get_ports {ddr4_dq[49]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B40                } [get_ports {ddr4_dq[50]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B37                } [get_ports {ddr4_dq[51]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B42                } [get_ports {ddr4_dq[52]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A37                } [get_ports {ddr4_dq[53]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B41                } [get_ports {ddr4_dq[54]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A38                } [get_ports {ddr4_dq[55]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B35                } [get_ports {ddr4_dq[56]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B32                } [get_ports {ddr4_dq[57]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A33                } [get_ports {ddr4_dq[58]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D33                } [get_ports {ddr4_dq[59]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A35                } [get_ports {ddr4_dq[60]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A34                } [get_ports {ddr4_dq[61]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C33                } [get_ports {ddr4_dq[62]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B33                } [get_ports {ddr4_dq[63]}]


#create_clock -name c0_sys_clk -period 4.998 [get_ports diff_clock_rtl_clk_p]