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- FPGA users signals;
- USB signals;
- Power signals;
- System reset signals.
Pin Labelling
FPGA user signals connected to B2B connectors are characterized by the "Vx_IO_yy_p" naming convention, where:
- Vx defines the FPGA bank (x = bank number);
- IO defines an "FPGA to B2B" signal type;
- yy defines a differential pair or signal number (yy = pair number);
- p defines a differential signal polarity (P = positive, N = negative); single ended signals do not have this field.
Remaining signals use custom names.
J4 connector pinout
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Overview
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