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title | J5 connector pin-out |
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J5 pin | Net | Type | FPGA pin | Net Length (mm) | J5 pin | Net | Type | FPGA pin | Net Length (mm) |
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1 | 5Vb2b | POW | - | - | 2 | 5Vb2b | POW | - | - | 3 | 5Vb2b | POW | - | - | 4 | 5Vb2b | POW | - | - | 5 | 5V | POW | - | - | 6 | /MR | SYS | - | - | 7 | B2B_D_P | USB | - | - | 8 | /RESET | SYS | - | - | 9 | B2B_D_N | USB | - | - | 10 | RESET | SYS | - | - | 11 | GND | GND | - | - | 12 | GND | GND | - | - | 13 | V3_IO_12 | SIO | T2 | 19.97 | 14 | V3_IO_16 | SIO | U1 | 10.26 | 15 | V3_IO_13 | SIO | T1 | 18.91 | 16 | V3_IO_17 | SIO | U3 | 11.74 | 17 | V2_IO_01 | SIO | V15 | 18.18 | 18 | V3_IO_18 | SIO | V1 | 9.72 | 19 | V3_IO_14 | SIO | AA2 | 16.26 | 20 | V3_IO_19 | SIO | V2 | 10.03 | 21 | V3_IO_15 | SIO | AB2 | 15.23 | 22 | V3_IO_20 | SIO | Y1 | 9.21 | 23 | GND | GND | - | - | 24 | GND | GND | - | - | 25 | V2_IO_01_N | DIO | AB6 | 10.68 | 26 | V3_IO_21 | SIO | Y2 | 8.73 | 27 | V2_IO_01_P | DIO | AA6 | 12.54 | 28 | V3_IO_22 | SIO | AB3 | 6.68 | 29 | V2_IO_02_P | DIO | Y7 | 13.32 | 30 | V3_IO_23 | SIO | Y3 | 8.38 | 31 | V2_IO_02_N | DIO | AB7 | 11.56 | 32 | V3_IO_24 | SIO | AB4 | 6.65 | 33 | V3_IO_27 | SIO | U8 | 8.41 | 34 | V3_IO_25 | SIO | AA4 | 7.51 | 35 | 3.3V | POW | - | - | 36 | 3.3V | POW | - | - | 37 | V2_IO_03_N | DIO | AB8 | 12.43 | 38 | V3_IO_26 | SIO | Y4 | 8.41 | 39 | V2_IO_03_P | DIO | AA8 | 13.01 | 40 | V2_IO_10_P | DIO | W6 | 9.20 | 41 | V2_IO_02 | SIO | AB12 | 12.62 | 42 | V2_IO_10_N | DIO | Y6 | 8.31 | 43 | GND | GND | - | - | 44 | GND | GND | - | - | 45 | V2_CLK_01_N | CIO | AB11 | 11.34 | 46 | V2_IO_11_N | DIO | Y8 | 8.09 | 47 | V2_CLK_01_P | CIO | Y11 | 12.64 | 48 | V2_IO_11_P | DIO | W9 | 9.10 | 49 | V2_IO_04_P | DIO | W15 | 14.63 | 50 | V2_IO_12_P | DIO | Y9 | 8.40 | 51 | V2_IO_04_N | DIO | Y16 | 12.42 | 52 | V2_IO_12_N | DIO | AB9 | 6.60 | 53 | 2.5V | POW | - | - | 54 | 2.5V | POW | - | - | 55 | V2_IO_05_N | DIO | U14 | 17.21 | 56 | V2_CLK_02_N | CIO | AB10 | 7.26 | 57 | V2_IO_05_P | DIO | T14 | 18.75 | 58 | V2_CLK_02_P | CIO | AA10 | 8.16 | 59 | V2_IO_06_P | DIO | AA14 | 12.39 | 60 | V2_IO_13_P | DIO | W11 | 11.39 | 61 | V2_IO_06_N | DIO | AB14 | 11.34 | 62 | V2_IO_13_N | DIO | Y10 | 10.30 | 63 | GND | GND | - | - | 64 | GND | GND | - | - | 65 | V2_IO_07_N | DIO | AB15 | 11.87 | 66 | V2_IO_14_N | DIO | Y12 | 9.80 | 67 | V2_IO_07_P | DIO | Y15 | 13.55 | 68 | V2_IO_14_P | DIO | W12 | 10.80 | 69 | V2_IO_08_P | DIO | AA16 | 12.61 | 70 | V2_IO_15_P | DIO | Y13 | 10.20 | 71 | V2_IO_08_N | DIO | AB16 | 11.72 | 72 | V2_IO_15_N | DIO | AB13 | 8.40 | 73 | 1.2V | POW | - | - | 74 | 1.2V | POW | - | - | 75 | V2_IO_09_N | DIO | AB18 | 11.91 | 76 | V2_IO_16_N | DIO | Y14 | 9.72 | 77 | V2_IO_09_P | DIO | AA18 | 12.57 | 78 | V2_IO_16_P | DIO | W14 | 10.72 | 79 | GND | GND | - | - | 80 | GND | GND | - | - |
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Signal integrity considration
Traces of differential signals pairs are routed symmetrically (as symmetric pairs).
Traces of differential signals pairs are NOT routed with equal length Difference (difference in signal lines length is negligible for used signal frequency.). For applications where traces length has to be matched or timing differences have to be compensated, Table 21 J4 and Table 22 J5 (above) list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.
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