SmartDesign components
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Template Revision 1.0 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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title | Design Revision History |
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Date | Libero | Project Built | Authors | Description |
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2020-09-xy | 12.4 | ?!?!?!?!?!?!?!?!?!?!?!!!!!!!?????? Namen des Archieves angeben
| Kilian Jahn | | 2018-02-26 | 11.8?!?!?!?!?!?!?!?!?!?!?!!!!!!!?????? | Smartberry_Webserver_Demo.zip | ?!?!?!?!?!?! | | 2020-05-11 | 2019.2 | TE0808-SK_DEMO1_noprebuilt-vivado_2019.2-build_11_20200511131530.zip
TE0808-SK_DEMO1-vivado_2019.2-build_11_20200511131516.zip | Mohsen Chamanbaz | |
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Release Notes and Know Issues
Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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anchor | Table_HWM |
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title | Hardware Modules |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0808ES1 es1_2gb REV03REV02 2GB | 64MB REV01 | 1 GBit / 128 MB | 256 kB | NA | NA |
Not longer supported by vivado | TE0808-ES2 | es2_2gb | REV04|REV03 | 2GB | Different DDR vendor | TEM0002-02-010C | smartberry | REV02 | REV01 | 1 GBit / 128 MB | 256 kB |
64MB Not longer supported by vivado | TE0808-2ES2 | 2es2_2gb | REV04|REV03 | 2GB | 64MB | NA | NA | Not longer supported by vivado |
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Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Design supports following carriersAdditional HW Requirements:
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title | Additional Hardware Carrier |
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Carrier ModelAdditional Hardware | Notes |
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TEBF0808 | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
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Additional HW Requirements:
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| Micro USB to USB Type A Cable | Power supply over USB. Programming the board. Communication Interface with the board. | ETH cable | Ethernet configured to use DHCP. Configuration for use of a static IP possible. | Lan to USB / Router | Optional HW for accessing the Web server |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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title | Additional HardwareDesign sources |
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Type | LocationAdditional Hardware | Notes | Board |
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Micro USB to USB Type A Cable | Power supply over USB. Programming the board. Communication Interface with the board. | ETH cable | Ethernet works with DHCP, but can be setup also manually | Lan to USB / Router | Optional HW for accessing the Web server | PMod / External IO | Optional HW, not utilized | SD card | Optioinal HW, not utilized |
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Libero | <design name>/block_design <design name>/constraints <design name>/ip_lib | Libero Project likely as zip-archieve /project generation by TE Scripts is not possible? | SoftConsole | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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title | Additional design sources |
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Prebuilt
For general structure and of the reference design, see Project Delivery - Xilinx devices
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- prebuilt files
- Template Table:
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TypeLocationNotes |
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
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title | Additional design sources |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Image | --- | Generic Linux kernel binary image file | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems | Device Tree Blob File | *.dtb | Contains a Device Tree Blob |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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title | Prebuilt files (only on ZIP with prebult content) |
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File | File-Extension | Description |
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Constrain files |
BIF*bif | File with description to generate Bin-File | BIN*.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Debian SD-Image | *.img | Debian Image for SD-Card |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Image | --- | Generic Linux kernel binary image file |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
Device Tree Blob File | *.dtb | Contains a Device Tree Blob |
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.sdc | Time constrain | Programming files |
| .ipd | Libero SoC in system programming via JTAG, not exportable |
| .stp / .dat | In system programming via JTAG |
| .dat / .stp / .spi | In system programming of SPI-slave |
| .spi | In system programming of Cortex-M3 | SmartDesign component files |
| .sdb / . cfx |
| Log files |
| .log / .rtp / .xml / .scv / .txt |
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| Simulation Files (*.mem *.bfm *.dat *.txt *.do) |
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| Designer directory - ADB files (Microsemi Designer project files), -_ba.SDF, _ba.v(hd), STP, TCL (used to run designer), impl.prj_des (local project file relative to revision), designer.log (logfile) *adb is the output |
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| hdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog. All these are the input files. |
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| phy_synthesis directory - _palace.edn, palace_top.rpt (palace logfile) and other files generated by PALACE simulation directory - meminit.dat, modelsim.ini files |
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| smartgen directory - GEN files and LOG files from configured generated cores |
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| synthesis directory - *.edn, *_syn.prj (Synplify log file), *.psp (Precision project file), *.srr (Synplify logfile), precision.log (Precision logfile), *.tcl (used to run synthesis) *.edn is the Output file. |
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| BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File |
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Image | --- | Generic Linux kernel binary image file |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Device Tree Blob File | *.dtb | Contains a Device Tree Blob |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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