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SmartDesign components

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Template Revision 1.0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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DateLiberoProject BuiltAuthorsDescription
2020-09-xy12.4?!?!?!?!?!?!?!?!?!?!?!!!!!!!??????
Namen des Archieves angeben
Kilian Jahn
  • Ported from 11.8
2018-02-2611.8?!?!?!?!?!?!?!?!?!?!?!!!!!!!??????Smartberry_Webserver_Demo.zip?!?!?!?!?!?!
  • Initial release
2020-05-112019.2TE0808-SK_DEMO1_noprebuilt-vivado_2019.2-build_11_20200511131530.zip
TE0808-SK_DEMO1-vivado_2019.2-build_11_20200511131516.zip		Mohsen Chamanbaz
  • initial release

Release Notes and Know Issues


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed

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64MB       
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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808
TEM0002-02-
ES1          
010CA     
es1_2gb      
smartberry
REV03
REV02 |
REV02 
2GB      
REV011 GBit / 128 MB256 kB       NA         NA               
Not longer supported by vivado       TE0808-ES2          es2_2gb      REV04|REV03 2GB      
Different DDR vendor
TEM0002-02-010CsmartberryREV02 | REV01 1 GBit / 128 MB256 kB       
64MB       
NA         NA               
Not longer supported by vivado                   TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                
NA


Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.


Design supports following carriersAdditional HW Requirements:

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Carrier ModelAdditional HardwareNotes
TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

Additional HW Requirements:

Board
Micro USB to USB Type A CablePower supply over USB. Programming the board. Communication Interface with the board.
ETH cableEthernet configured to use DHCP. Configuration for use of a static IP possible.
Lan to USB / RouterOptional HW for accessing the Web server


Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationAdditional HardwareNotesBoard
Micro USB to USB Type A CablePower supply over USB. Programming the board. Communication Interface with the board.
ETH cableEthernet works with DHCP, but can be setup also manually
Lan to USB / RouterOptional HW for accessing the Web server
PMod / External IOOptional HW, not utilized
SD cardOptioinal HW, not utilized

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Libero<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Libero Project likely as zip-archieve /project generation by TE Scripts is not possible?
SoftConsole<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation


Additional Sources

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titleAdditional design sources

Prebuilt

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  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

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DSDesign sources
  • prebuilt files
  • Template Table:


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    • Prebuilt files

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Type

    • File

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    • File-Extension

Notes

    • Description

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration

Additional Sources

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titleAdditional design sources

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    • BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Image---Generic Linux kernel binary image file
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

      Device Tree Blob File*.dtbContains a Device Tree Blob

Prebuilt

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  • prebuilt files
  • Template Table:




BIN
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File

File-Extension

Description

Constrain files
BIF


PDC-File
*
.
bif
pdcPin constrain file
PDS
File with description to generate Bin-File
-File
*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileDebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formatsHardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)Image---Generic Linux kernel binary image fileSoftware-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Device Tree Blob File*.dtbContains a Device Tree Blob Scroll Title
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.sdcTime constrain
Programming files

.ipdLibero SoC in system programming via JTAG, not exportable

.stp / .datIn system programming via JTAG

.dat / .stp / .spiIn system programming of SPI-slave

.spiIn system programming of Cortex-M3
SmartDesign component files

.sdb / . cfx
Log files

.log / .rtp / .xml / .scv / .txt






Simulation Files (*.mem *.bfm *.dat *.txt *.do)







Designer directory

- ADB files (Microsemi Designer project files),
-_ba.SDF, _ba.v(hd), STP, TCL (used to run designer),
impl.prj_des (local project file relative to revision),
designer.log (logfile) *adb is the output






hdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog. All these are the input files.




phy_synthesis directory
- _palace.edn, palace_top.rpt (palace logfile) and other files generated by PALACE simulation directory
- meminit.dat, modelsim.ini files




smartgen directory - GEN files and LOG files from configured generated cores




synthesis directory
- *.edn, *_syn.prj (Synplify log file),
*.psp (Precision project file),
*.srr (Synplify logfile),
precision.log (Precision logfile),
*.tcl (used to run synthesis)
*.edn is the Output file.







BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileDebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging InterfaceDiverse Reports---Report files in different formatsHardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project FileOS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)Image---Generic Linux kernel binary image file
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Device Tree Blob File*.dtbContains a Device Tree Blob


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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