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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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| anchor | Table_HWM |
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| title | Hardware Modules |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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| TEM0002-02-010CA | smartberry | REV02 | REV01 | 1 GBit / 128 MB | 256 kB | NA | NA | Different DDR vendor | | TEM0002-02-010C | smartberry | REV02 | REV01 | 1 GBit / 128 MB | 256 kB | NA | NA | NA |
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<<============== ABKLÄREN OB BEIDE HW-Revisionen unterstütz werden
Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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| anchor | Table_DS |
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| title | Design sources |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Type | Location | Notes |
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| Libero | <design name>/block_design
<design name>/constraints
<design name>/ip_lib | Libero Project likely as zip-archieve /project generation by TE Scripts is not possible? | | SoftConsole | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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| Scroll Title |
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| anchor | Table_PF |
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| title | Prebuilt files (only on ZIP with prebult content) |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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File | File-Extension | Description |
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| Constrain files |
PDC-File | PDS-File |
| .sdc | Time constrain | | Programming files |
| .ipd | Libero SoC in system programming via JTAG, not exportable |
| .stp / .dat | In system programming via JTAG |
| .dat / .stp / .spi | In system programming of SPI-slave |
| .spi | In system programming of Cortex-M3 | | SmartDesign component files |
| .sdb / . cfx |
| | Log files |
| .log / .rtp / .xml / .scv / .txt |
| | Simulation Files |
(* * * * *)- ADB files ( |
| .adb | Microsemi Designer project files |
),-_baSDF, _, STP, TCL (used | / .stp / .tcl | Script-files to run designer |
),impl (local project file relative to revision),designer.log (logfile) *adb is the outputhdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog. All these are the input files. | phy_synthesis directory
- _palace.edn, palace_top.rpt (palace logfile) and other files generated by PALACE simulation directory
- meminit.dat, modelsim.ini files | smartgen directory - GEN files and LOG files from configured generated cores | synthesis directory
- *.edn, *_syn.prj (Synplify log file),
*.psp (Precision project file),
*.srr (Synplify logfile),
precision.log (Precision logfile),
*.tcl (used to run synthesis)
*.edn is the Output file. | | Local revision project file | | Input source files (hdl directory ) |
| .vhd / .v / .h |
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| .edn, / _syn.prj / .srr | Synplify log file |
| .psp | Precision project file |
| precision.log | Precision logfile |
| .tcl | Script-files to runsynthesis |
| .edn | Synthesis output file | | Generally software related |
| BIF-File | *.bif | File with description to generate Bin-File | | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | | BIT-File | *.bit | FPGA (PL Part) Configuration File | Software-Application-File |
| *.elf | Software Application file for |
Zynq or MicroBlaze | Processor Systems | | Device Tree Blob File | *.dtb | Contains a Device Tree Blob |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx Libero/SoftConsole version. Do never use different Versions versions of Xilinx Microsemi Software for the same Project.
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Reference Design is available on:
- TE0808 TEM0002 "SK DEMO1" Reference DesignWebserver Demo" Reference Design <<================ ADD / Convert to - LINK
Design Flow
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