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Template Revision 21.8 0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 TEI0006 Test Board"


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DateQuartusProject BuiltAuthorsDescription
2020-10-1919.1 Lite

TEI0010-test_board_noprebuilt-quartus_19.1.0-20201019102006.zip

TEI0010-test_board-quartus_19.1.0-20201019101953.zip

Thomas Dück
  • script update
  • bugfixes
2020-05-1319.1 Lite

TEI0010-test_board_noprebuilt-quartus_19.1.0-20200513105940.zip

TEI0010-test_board-quartus_19.1.0-20200513110730.zip

Thomas Dück
  • 19.1 update
2019-11-1118.1

TEI0010-test_board_noprebuilt-quartus_18.1-20191111104210.zip

TEI0010-test_board-quartus_18.1-20191111104330.zip

Thomas Dück
  • create project with TE scripts
  • new board variants
2019-04-1718.1TEI0010-02-08-C8-test_board-quartus_18.1-20190417.zipThomas Dück
  • initial release


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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-SOPC Information File*.bifsopcinfoFile with description to generate Bin-Fileof the .qsys file to create software for the target hardware
      SRAM Object BIN- File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)sofRam configuration file
      Programmer Object BIT- File*.bitpofFPGA (PL Part) Configuration FileDebugProbes-Fileconfiguration file
      JTAG indirect configuration file*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      jicFlash configuration file
      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

      application for NIOS II processor system




Scroll Title
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File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
Programmer Object File*.pofFPGA configuration file
Diverse Reports---Report files in different formats
Software Application File*.elfSoftware application for NIOS II processor system


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Reference Design is available on:

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  1. Prepare Hardware like described on section Programming 77529790
  2. Connect UART USB (most cases same as JTAG)

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Note:

  • Description of Block Design , Constrains- Project, Block Design - Platform Desginer, ... BD Block Design Pictures from Export...

Block Design

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titleBlock Design - Project
Block Design - test_board.bdf

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----------------------------------------------------------

General Example:

hello_tei0006

Hello TEI0006 is a Quartus Hello World example as endless loop instead of one console output.

Template location: <design_name>/source_files/software/

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DateDocument Revision

Authors

Description

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infoTypeModified date
dateFormatyyyy-MM-dd
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infoTypeCurrent version
dateFormatyyyy-MM-dd
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infoTypeModified by
typeFlat

  • script update
  • bugfixes
2020-05-13v.4Thomas Dück
  • 19.1 release
2019-11-11v.3Thomas Dück
  • change design to TE scripts
  • new variants
2019-04-17v.1Thomas Dück
  • Initial release 18.1
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dateFormatyyyy-MM-dd
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