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- Plug the TE0835 module on the TEB0835 carrier board
- Connect the micro USB cable to the J29 connector
- Plug the power supply cable to the J19 connector
- Plug the prepared SD card on the SD card socket (J28)
- Connect a cable with SMA or SMT connector to one of the DAC connector( for example DAC0 J9) and feed it back to the related ADC input (for example ADC0 J1)
- (optional) A signal generator can be used to feed desired sinal to ADC input.
- (optional) An oscilloscope can be used to monitor the output signal of DAC.
Designator | PIN | ADC/DAC Tile | Footprint |
---|---|---|---|
J1 | ADC0_IN | 224 ADC0 | SMA |
J2 | ADC1_IN | 224 ADC1 | SMT |
J3 | ADC2_IN | 225 ADC0 | SMA |
J4 | ADC3_IN | 225 ADC1 | SMT |
J5 | ADC4_IN | 226 ADC0 | SMA |
J6 | ADC5_IN | 226 ADC1 | SMT |
J7 | ADC6_IN | 227 ADC0 | SMA |
J8 | ADC7_IN | 227 ADC1 | SMT |
J9 | DAC0_OUT | 228 Pair0,1 | SMA |
J10 | DAC1_OUT | 228 Pair0,1 | SMT |
J11 | DAC2_OUT | 228 Pair2,3 | SMA |
J12 | DAC3_OUT | 228 Pair2,3 | SMT |
J13 | DAC4_OUT | 229 Pair0,1 | SMT |
J14 | DAC5_OUT | 229 Pair0,1 | SMT |
J15 | DAC6_OUT | 229 Pair2,3 | SMT |
J16 | DAC7_OUT | 228 Pair2,3 | SMT |
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- Prepare HW like described on section TE0835 Test Board#Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynqmp Zynqmp RFSoC Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR - Open the RF Analyzer GUI
- Click on Connect
- Adjust the desired JTAG frequency (for example 30MHZ)
- Give the generated bitstream file path
- Click on Download Bitstream on the FPGA
- When downloading is the downloading finished, click on Select Target
- After the initilalisation, all ADCs/DACs tile tiles are visible
- Click the on desired DAC tile and choose a DAC (for example DAC0)
- Adjust the desired DAC property properties (for example output frequency)
- Click on Generation Generate to generate the signal in output of DAC
- Click on the related ADC tile and choose the related ADC (for example ADC0)
- Click on Acquisition Acquire to aqcuire the input signal
- The spectum of the DAC output signal can be seen now. The signal can be visible in time domain too.
- Tip: In Window menu click on Multiview to see all of DACs and ADCs simultaneously.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB2.0 device
- Option Features
- Webserver to get access to Zynqmp RFSoC
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
- Webserver to get access to Zynqmp RFSoC
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Template location: ./sw_lib/sw_apps/
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Software Design - PetaLinux
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5395 on the RFSoC module configuration
- Si5395 on the TEB0835 carrier board configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0835
Hello TE0835 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
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Webserver application accemble for Zynqmp RFSoC access. Need busybox-httpd
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