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| Scroll Title |
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| anchor | Table_SIP_ETH |
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| title | Gigabit Ethernet PHY to Zynq SoC connectionsinformation |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Name | Connected to | Signal Description | Note |
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| PHY_MDI0...3 | B2B, J17 | Media Data |
| | PHY_LED0...1 | B2B, J17 | Speed/Link Indicators LED | Yellow/Green |
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| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U12 Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | JTAG_TCK | B2B, J17 Pin Header, J40 | JTAG interface | | ADBUS1 | JTAG_TDI | B2B, J17 Pin Header, J40 | | ADBUS2 | JTAG_TDO | B2B, J17 Pin Header, J40 | | ADBUS3 | JTAG_TMS | B2B, J17 Pin Header, J40 | | BDBUS0 | UART0_RX | B2B, J17 | UART | | BDBUS1 | UART0_TX | B2B, J17 | UART | | EECS/EECLK/EEDATA | BDBUS2 | EEPROM, U15 | FTDI configuration | | DM/DP | D_N/D_P | Micro USB2.0, J29 | FTDI Input |
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There is a programmable clock generator on-board (U5) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J20. The I2C Address is 0x68.
| Scroll Title |
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| anchor | Table_OBP_PCLK |
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| title | Programmable Clock Generator Inputs and Outputs |
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| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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U5 Pin
| Signal | Connected to | Direction | Note |
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| IN0 | CLKIN0 | Oscillator, U6 | Input |
| | IN1 | CLKIN1 | UMCC Connector, J36 | Input |
| | IN2 | CLKIN2 | UMCC Connector, J37 | Input |
| | IN3 | FB | Programmable Clock Generator, U5 | Input/Output |
| | XA/XB | CLK0_XA/XB | Oscillator, Y1 | Input |
| | IN_SEL0...1 | DSPLL0_SEL0...1 | I2C Switch, U7 DIP Switch, S2 | Input |
| | nINTR | DSPLL0_INTR_N | I2C Switch, U7 | Input |
| | nLOL | DSPLL0_LOL_N | Green LED, D12 | Input |
| | nRST | DSPLL0_RST_N | 1.8 V | Input |
| | SCLK | DSPLL0_SCL | I2C Switch, U7 | Input |
| | SDA/SDIO | DSPLL0_SDA | I2C Switch, U7 Pin Header, J41 | In/Out |
| | INTR | PLL_INTR_N | B2B, J17 | Output |
| | OUT0A | CLKOUT0A | B2B, J17 | Output |
| | OUT0 | CLKOUT0_P | B2B, J17 | Output |
| | OUT1 | PLLCLK1 | UMMC, J27 | Output |
| | OUT2 | PLLCLK2 | UMMC, J20 | Output |
| | OUT3 | PLLCLK3 | UMMC, J32 | Output |
| | OUT4 | PLLCLK4 | UMMC, J33 | Output |
| | OUT5 | PLLCLK5 | UMMC, J34 | Output |
| | OUT6 | PLLCLK6 | UMMC, J35 | Output |
| | OUT7 | CLKOUT7 | UMMC, J38 | Output |
| | OUT8 | CLKOUT8 | UMMC, J42 | Output |
| | OUT9 | CLKOUT9 | UMMC, J43 | Output |
| | OUT9A | CLKOUT9A | Programmable Clock Generator, U5 | Output |
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