Page History

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#1 Added generic options for PUDC and Boot Mode

Type: Enhancement
Reason:Pullup or pulldown for Provide easy option to select pullup/down for CPLD IO pins selectable to change the boot mode and PUDC for custom request easierconnected to Zynq Boot Mode and PUDC pins.
Impact: None. Default CPLD source code is still PUDC low (Zynq pullups activated) and Boot Mode QSPI/SD.

#2 Set pin associated with MIO7 to Pullnone

Type: Enhancement
Reason: HW Pulldown on carrier for Bank0 Voltage Hardware pulldown on module installed for Zynq Bank0 voltage selection (3.3V). Further pulling unnecessary.
Impact: None.

#3 Adding internal 3.3V enable signal en_3v3_int

Type: Enhancement
Reason: To connect 3.3V to enable pin of the 3.3V regulator after the core Drive signals only high after core voltage is up.
Impact:  To achive None, improved power sequencing correctly.

#4 Set JTAG C_* signals high impedance until 3.

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3V is enabled

Type: Enhancement
Reason: JTAG pins connected to Zynq are high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#5 Boot mode pins

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set to GND or high impedance until en_3v3_int

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is high

Type: Enhancement
Reason: Boot Mode pins connected to Zynq are should be high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#6 MIO14,15 high impedance until en_3v3_int

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is high

Type: Enhancement
Reason: UART pins that connected to Zynq connected are high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#7 Improved JTAG time

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constraints

Type: Enhancement
Reason: Signal propagtion propagation constraints to improve JTAG on high trafficfor JTAG were not implemented.
Impact: No Impact None, improve JTAG connectionimproved JTAG reliability at high speeds.

#8 JTAG drive line adjustment

Type: Enhancement
Reason: Driver constraints to improve JTAG on high traffic
Impact: No ImpactNone, improve improved JTAG connection.

#9 Bugfix I2C to GPIO module (I2C_to_GPIO.v)

Type: Bugfix
Reason: Communicate Communication with GPIO subsystem via I2C was not possible.
Impact:  Reading and writing data from/to CPLD internal registers via I2C bus works correctly.

#10 Changed Firmware Identifier to REV06

Type: Update
Reason: Show correct firmware revision with Trenz FSBL.
Impact: None. Actual firmware revision is shown with Trenz FSBL.

More information about System Controller can be found here: TE0720 System Controller. The new firmware is compatible with PCB revisions REV02 and REV03 of TE0720. Actual REV06 programming file of the Firmware is available in the Downolad area. The REV05 programming files are moved to the archive, available on the same Download area page.

Method of Identification

All TE0720-03 SoMs noted in the column replacement are delivered with REV06 CPLD firmware.

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