Page History
Template Revision 2.7 - on construction
HTML |
---|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
...
hidden | true |
---|---|
id | Comments |
Important General Note:
...
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
...
Figure template (note: inner scroll ignore/only only with drawIO object):
...
anchor | Figure_xyz |
---|---|
title | Text |
Scroll Ignore |
---|
Create DrawIO object here: Attention if you copy from other page, use |
Scroll Only |
---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
...
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
...
anchor | Table_xyz |
---|---|
title | Text |
Scroll Table Layout | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Scroll pdf ignore | ||||
---|---|---|---|---|
Table of contents
|
Overview
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info
Key Features
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Excerpt |
---|
|
Revision History
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
...
anchor | Table_DRH |
---|---|
title | Design Revision History |
...
...
...
...
- initial release
...
anchor | Table_KI |
---|---|
title | Known Issues |
Scroll Table Layout | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Requirements
Software
...
...
...
...
Hardware
...
...
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
- list of software which was used to generate the design
...
...
Design supports following carriers:
...
...
...
...
...
...
- Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
...
- Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers
- Used as reference carrier.
...
- Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
...
- Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
...
- Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
- No SD Slot available, pins goes to Pin Header
- For TEBA0841 REV01, please contact TE support
...
- mportant: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
Additional HW Requirements:
...
...
Content
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
For general structure and of the reference design, see Project Delivery - Xilinx devices
...
...
...
...
...
Additional Sources
...
anchor | Table_ADS |
---|---|
title | Additional design sources |
...
...
...
...
Prebuilt
...
...
...
...
...
...
...
...
SREC-File
...
*.srec
...
...
Debian SD-Image
...
*.img
...
Debian Image for SD-Card
...
MCS-File
...
*.mcs
...
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
...
MMI-File
...
*.mmi
...
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
...
...
...
...
...
...
...
...
...
...
...
...
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Reference Design is available on:
Design Flow
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also TE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from "/os/petalinux"
- XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size"
- "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis - (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Get prebuilt boot binaries
...
...
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0823" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Artikel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
SD
Use this description for CPLD Firmware with SD Boot selectable.
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
...
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
...
- User Name: root
- Password: root
...
- I2C 0 Bus type: i2cdetect -y -r 0
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB2.0 device
...
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
...
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Control:
- GTR Power: set X0=0 and X1=1 to disable GTR Power
- USER LED: On/OFF
Monitoring:
- SI5338_CLK0 Counter: 200MHz with example Design
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
- Set radix from VIO signals to unsigned integer.
- ETH PHY LEDs
Scroll Title | ||||
---|---|---|---|---|
| ||||
System Design - Vivado
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Block Design
PS Interfaces
...
...
...
Software Design - Vitis
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For SDK project creation, follow instructions from:
Application
...
hidden | true |
---|---|
id | Comments |
----------------------------------------------------------
FPGA Example
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
...
...
...