Page History

Important General Note:

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Figure template (note: inner scroll ignore/only only with drawIO object):

Overview

Overview

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info

Key Features

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0821-info

Key Features

Revision History

• initial release

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

^*used as reference

Design supports following carriers:

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers    
• Used as reference carrier.

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers

• Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
• No SD Slot available, pins goes to Pin Header
• For TEBA0841 REV01, please contact TE support

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

^*used as reference

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

Notes :

File

File-Extension

Description

Debian SD-Image

*.img

Debian Image for SD-Card

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

File

File-Extension

Description

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0821 "Test Board" Reference Design

Design Flow

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Page properties
hidden true id Comments
Notes : Basic Design Steps Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

prebuilt files Template Table: Scroll Title anchor Table_PF title-alignment center title Prebuilt files Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

Scroll Title
anchor Table_PF title-alignment center title Prebuilt files (only on ZIP with prebult content)
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0821 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides

• Vivado Projects - TE Reference Design

• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"

3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart

   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

7. Generate Programming Files with Vitis (recommended)

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

Code Block
language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

8. Press 0 and enter to start "Module Selection Guide"
9. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.


optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

Note
Note: Select correct one, see also Vivado Board Part Flow

Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

Code Block
language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
TE::hw_build_design -export_prebuilt

Info
Using Vivado GUI is the same, except file export to prebuilt folder.

10. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"

    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

11. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
12. Copy PetaLinux build image files to prebuilt folder

    copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
    

    Info
    "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

    Page properties

    hidden	true
    id	Comments

    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

    for ZynqMP
    

    copy u-boot.elf,
    1. Copy PetaLinux build image files to prebuilt folder

       • copy u-boot.elf, system.dtb,

    1. • bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
         

    for ...

    • ...

    Generate Programming Files with Vitis

    Code Block
    language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    Note
    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

Launch

1. 1. • Info
        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

        
        

        Page properties
        hidden true id Comments
        This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for Microblaze ...

        
        

   2. Generate Programming Files with Vitis

      Code Block
      language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      
      

      Note
      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

      
      

2. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Programming

Programming

Xilinx documentation for programming and debugging: Vivado/SDKVitis/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell

2. Press 0 and enter to start "Module Selection Guide"

   1. Select assembly version

   2. Validate selection

   3. Select Create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

      Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0821 (optional)

   
   

   Note
   To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

   
   

3. Copy image.ub and boot.scr on SD or USB

   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries

   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"

4. Set Boot Mode to QSPI-Boot and insert SD or USB.

   • Depends on Carrier, see carrier TRM.

SD-Boot mode

Use this description for CPLD Firmware with SD Boot selectable.

1. Copy image.ub, boot.src and Boot.bin on SD

   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries

   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"

2. Set Boot Mode to SD-Boot.

   • Depends on Carrier, see carrier TRM.

3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming

2. Connect UART USB (most cases same as JTAG)

3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. Power On PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

Linux

1. Open Serial Console (e.g. putty)

   1. Speed: 115200

   2. Select COM Port
      

      Info
      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

      
      

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   # password disabled petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)

   
   

4. Option Features

   • Webserver to get access to Zynq

     • insert IP on web browser to start web interface

   • init.sh scripts

     • add init.sh script on SD, content will be load automatically on startup (template included in

       ./misc/SD

       "<project folder>\misc\SD")

   
   

Vivado HW Manager

Monitoring:

Monitoring:

• SI5338_CLK0 Counter:

  .

  • Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz for CLK signals

• SI5338 CLK1 is configured

  to 

  to 200MHz by default

  amd

  and SI5338 CLK3 is configured to 125MHz by default.

Control:

• Simple loopback vio_test_in test_out

• LED over X0/X1 , see TE0821 CPLD#LED

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN E5 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property PACKAGE_PIN C3 [get_ports {SI5338_CLK3_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK3_D_clk_p[0]}]

set_property PACKAGE_PIN B1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN C1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

set_property PACKAGE_PIN G8 [get_ports {PHY_LED[0]}]
set_property PACKAGE_PIN E9 [get_ports {PHY_LED[1]}]
set_property PACKAGE_PIN D9 [get_ports {PHY_LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {PHY_LED[*]}]

set_property PACKAGE_PIN A5 [get_ports {TEST_IN[0]}]
set_property PACKAGE_PIN B6 [get_ports {TEST_OUT[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_IN[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_OUT[0]}]

Software Design - Vitis

_ports {TEST_OUT[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_IN[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {TEST_OUT[0]}]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

For SDK project creation, follow instructions from:

Vitis

Application

zynqmp_fsbl

TE modified

2022.2 FSBL

General:

• Modified Files: xfsbl_main.c,

• xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_

• xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device

• • Name

Module Specific:

• Add Files: all TE Files start with te_*
  

• READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
• CPLD access
• Read CPLD Firmware and SoC Type
• Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
• Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0821

Hello TE0821 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot
Changes:

• • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0821

Hello TE0821 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
• Identification
  • CONFIG_SUBSYSTEM_HOSTNAME="trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0821"

U-Boot

Start with petalinux-config -c u-boot
Changes:

• MAC from eeprom together with uboot and device tree settings:
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_ZYNQ_MAC_IN_EEPROM is not set
  • CONFIG_NET_RANDOM_ETHADDR is not set
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x4040000
• Identification
  • CONFIG_IDENT_STRING=" TE0821"

Change platform-top.h:

#include <configs/xilinx_zynqmp.h>
#no changes

Device Tree

/include/ "system-conf.dtsi"

/*----------------------- SD1 sd2.0 -----------------------*/
&sdhci1 {
    disable-wp;
    no-1-8-v;
};


/*----------------------- USB 2.0 only --------------------*/
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
    snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};

&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};


/*------------------------- ETH PHY -----------------------*/
&gem3 {
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*------------------------- QSPI ------------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;

CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Change platform-top.h: