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| Scroll Title |
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| title | Module B2B FPGA-Banks and Voltages |
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| Scroll Table Layout |
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| orientation | landscape |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Group | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | special |
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| Module Model | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage | Bank | IOs | Type | Voltage |
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| | TE0710 | B15 | 48 | HR | VCCIOA | - | - | - | - | - | - | - | - | B34 | 50 | HR | VCCIOD | B16 | 6 | HR | 3.3V | B14 | 8 | HR | 3.3V | 2x 100Mbit ETH |
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| | TE0711 | B15 | 48 | HR | VCCIOA | B34 | 36 | HR | VCCIOB | B14 | 18 | HR | 3.3V | B35 | 50 | HR | VCCIOD | B16 | 6 | HR | 1.8V | B14 | 8 | HR | 3.3V | B34 | 8 | HR | VCCIOB | B34(4) | USB |
| | TE0712 | B16 | 48 | HR | VCCIOA | B13 | 20 | HR | VCCIOB | B14 | 18 | HR | 3.3V | B15 | 50 | HR | VCCIOD | B13 | 6 | HR | VCCIOB | B14 | 8 | HR | 3.3V | 1x 100Mbit ETH / B13 | 4 | HR | VCCIOB |
| B14 | 4x GTP on G2 | | TE0713 |
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| 4x GTP on G2 | TE0715 -xx-15
with Z-7015
Z-7012S
| B13 | 48 | HR | VCCIOA | B34 | 16 | HR | VCCIOC | B34 | 18 | HR | VCCIOC | B35 | 50 | HR | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB | 4x GTP on G2 | TE0715-xx-30
with Z-7030 | B13 | 48 | HR | VCCIOA | B34 | 16 | HP | VCCIOC | B34 | 18 | HP | VCCIOC | B35 | 50 | HP | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB | 4x GTP on G2 | | TE0720 | B35 | 48 | HR | VCCIOA | B34 | 36 | HR | VCCIOB | B33 | 18 | HR | VCCIOC | B13 | 50 | HR | VCCIOD | B501 | 6 | MIO | 1.8V | B500 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB |
| | TE0820* | B66 | 48 | HP | VCCIOA | B65 | 16 | HP | VCCIOC | B65 | 18 | HP | VCCIOC | B64 | 50 | HP | VCCIOD | B501 | 6 | MIO | 3.3V | B501 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB | 4x GTR on G2 | | TE0821* | B26 | 48 | HD | VCCIOA | B65 | 16 | HP | VCCIOC | B65 | 18 | HP | VCCIOC | B24 | 48 | HD | VCCIOD | B501 | 6 | MIO | 3.3V | B501 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB | 4x GTR on G2 | | TE0823* | B66 | 48 | HP | VCCIOA | B65 | 16 | HP | VCCIOC | B65 | 18 | HP | VCCIOC | B64 | 50 | HP | VCCIOD | B501 | 6 | MIO | 3.3V | B501 | 8 | MIO | 3.3V | 1x Gbit ETH |
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| SGMII | USB | 4x GTR on G2 | | TE0741 | B13 | 48 | HR | VCCIOA | B16 | 16 | HR | VCCIOB | B15 | 18 | HR | VCCIOC | B12 | 50 | HR | VCCIOD | 1x GTX | 1 Lane |
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| B14 | 8 | HR | 3.3V | 2x GTX | 2 Lanes |
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| 1x GTX |
| 4x GTX on G2 | | TE0742* |
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| | TE0841 | B64 | 48 | HR | VCCIOA | B66 | 16 | HP | VCCIOB | B68 | 18 | HP | VCCIOC | B67 | 50 | HP | VCCIOD | 1x GTH | 1 Lane |
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| B65 | 8 | HR | 3.3V | 2x GTH | 2 Lanes |
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| 1x GTH |
| 4x GTH on G2 | | TE0842* |
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I/O resource comparison for all 4x5 modules. There are maximum 4 user supplied I/O voltages (VCCIOA, VCCIOB, VCCIOC and VCCIOD). *Attention: Maximum supply voltage for HP banks is 1.8V. |
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| Scroll Title |
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| title | 4x5 Module Controller IOs |
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| Scroll Table Layout |
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| orientation | landscape |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Name | Module B2B Pin | Carrier B2B Pin | Direction (Module view) | Description | Recommendation |
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| JTAGSEL | JM1-89 | JB1-90 | in | JTAG Chain multiplexer. Low FPGA, High CPLD. For module with CPLD only. | Connect Pulldown on carrier.
DIP switch possible. | | SC_EN1 | JM1-28 | JB1-27 | in | Module power. Set high to enable module power. Note: Power management depends on module. Sometimes this is a only used as Power ON Reset like SC_nRST | Connect Pullup on carrier.
DIP switch possible | | SC_NOSEQ | JM1-7 | JB1-8 | in / inout | Module Power management. Set high to disable CPLD power management. Note: Power management depends on module and not all modules support extended power management with CPLD. | Connect Pullup or Pulldown force to GND over zero ohm resistor on carrier.
DIP switch possible. | | SC_PGOOD | JM1-30 | JB1-29 | out / inout | Power Good signal. Is Low, if SC_EN1 is set to zero or if power is not ready, otherwise high impedance output. Note: Power management depends on module.
On newer Firmware SC_PGOOD will be used as Additionally Boot Mode Pin. | Connect Pullup on carrier.
Do not use this signal to enable FPGA Bank voltages. It's only for monitoring. To Enable FPGA Banks, use 3.3V(PWR_M1) or 1.8V(PWR_M2) module output. | | SC_BOOTMODE | JM1-32 | JB1-31 | in | Boot Mode selection Pin for Zynq module only. Default low for primary SD boot and high for primary QSPI boot. Note: Depends also on module CPLD firmware | Connect Pullup on carrier.
DIP switch possible. | | SC_nRST | JM2-18 | JB2-17 | in | Low active module reset. Pin force Power one reset on FPGA/SoC. Note: Depending from module CPLD or voltage supervisor is used. | Connect Pullup on carrier.
DIP switch possible. |
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Remove 4x5 module
| Widget Connector |
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| url | https://www.youtube.com/watch?v=uisv2dWbktc |
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- Controller IOs are 3.3V IOs
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Remove 4x5 module
4 x 5 SoMs Handling and Usage Precautions
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Compatibility Guide
Ethernet LED'S
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Solution A: connect to 3.3V out from the module, option compatible to all modules except those with HP banks (TE0715-01-30)
Solution B: connect to 1.8V out from the module, option compatible with all modules.
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