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Scroll Title
titleModule B2B FPGA-Banks and Voltages

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Group123456789special
Module ModelBankIOsTypeVoltageBankIOsTypeVoltageBankIOsTypeVoltageBankIOsTypeVoltageBankIOsTypeVoltageBankIOsTypeVoltageBankIOsTypeVoltage


TE0710B1548HRVCCIOA--------B3450HRVCCIODB166HR3.3VB148HR3.3V2x 100Mbit ETH





TE0711B1548HRVCCIOAB3436HRVCCIOBB1418HR3.3VB3550HRVCCIODB166HR1.8VB148HR3.3VB348HRVCCIOBB34(4)USB
TE0712

B16

48HRVCCIOAB1320HRVCCIOBB1418HR3.3VB1550HRVCCIODB136HRVCCIOBB148HR3.3V

1x 100Mbit ETH / B13

4HRVCCIOB
B144x GTP on G2
TE0713





























4x GTP on G2

TE0715

-xx-15

with Z-7015

B1348HRVCCIOAB3416HRVCCIOCB3418HRVCCIOCB3550HRVCCIODB5016MIO1.8VB5008MIO3.3V1x Gbit ETH


SGMIIUSB4x GTP on G2
TE0715-xx-30
with Z-7030
B1348HRVCCIOAB3416HPVCCIOCB3418HPVCCIOCB3550HPVCCIODB5016MIO1.8VB5008MIO3.3V1x Gbit ETH


SGMIIUSB4x GTP on G2
TE0720B3548HRVCCIOAB3436HRVCCIOBB3318HRVCCIOCB1350HRVCCIODB5016MIO1.8VB5008MIO3.3V1x Gbit ETH


SGMIIUSB
TE0820*B6648HPVCCIOA B6516 HP VCCIOC B6518 HP VCCIOCB6450 HPVCCIODB5016MIO3.3V B5018MIO3.3V1x Gbit ETH


 SGMII USB4x GTR on G2
TE0821*B2648HDVCCIOA B6516 HP VCCIOC B6518 HP VCCIOCB2448HDVCCIODB5016MIO3.3V B5018MIO3.3V1x Gbit ETH


 SGMII USB4x GTR on G2
TE0823*B6648HPVCCIOA B6516 HP VCCIOC B6518 HP VCCIOCB6450 HPVCCIODB5016MIO3.3V B5018MIO3.3V1x Gbit ETH


 SGMII USB4x GTR on G2
TE0741B1348HRVCCIOAB1616HRVCCIOBB1518HRVCCIOCB1250HRVCCIOD1x GTX1 Lane

B148HR3.3V2x GTX2 Lanes

1x GTX
4x GTX on G2
TE0742*






























TE0841B6448HRVCCIOAB6616HPVCCIOBB6818HPVCCIOCB6750HPVCCIOD1x GTH1 Lane

B658HR3.3V2x GTH2 Lanes

1x GTH
4x GTH on G2
TE0842*






























I/O resource comparison for all 4x5 modules. There are maximum 4 user supplied I/O voltages (VCCIOA, VCCIOB, VCCIOC and VCCIOD).

*Attention: Maximum supply voltage for HP banks is 1.8V.

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Scroll Title
title4x5 Module Controller IOs

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NameModule B2B PinCarrier B2B PinDirection (Module view)DescriptionRecommendation
JTAGSELJM1-89JB1-90inJTAG Chain multiplexer. Low FPGA, High CPLD.  For module with CPLD only.

Connect Pulldown on carrier.
DIP switch possible.

SC_EN1JM1-28JB1-27inModule power. Set high to enable module power. Note: Power management depends on module. Sometimes this is a only used as Power ON Reset like SC_nRSTConnect Pullup on carrier.
DIP switch possible
SC_NOSEQJM1-7JB1-8in / inoutModule Power management. Set high to disable CPLD power management. Note: Power management depends on module and not all modules support extended power management with CPLD.Connect Pullup or Pulldown force to GND over zero ohm resistor on carrier.
DIP switch possible.
SC_PGOODJM1-30JB1-29out / inoutPower Good signal. Is Low, if SC_EN1 is set to zero or if power is not ready, otherwise high impedance output. Note:  Power management depends on module.Connect Pullup on carrier.
Do not use this signal to enable FPGA Bank voltages. It's only for monitoring. To Enable FPGA Banks, use 3.3V(PWR_M1) or 1.8V(PWR_M2) module output. 
SC_BOOTMODEJM1-32JB1-31inBoot Mode selection Pin for Zynq module only. Default low for primary SD boot and high for primary QSPI boot. Note: Depends also on module CPLD firmwareConnect Pullup on carrier.
DIP switch possible.
SC_nRSTJM2-18JB2-17inLow active module reset. Pin force Power one reset on FPGA/SoC. Note: Depending from module CPLD or voltage supervisor is used.Connect Pullup on carrier.
DIP switch possible.


Note

It's planned to use SC_PGOOD of also additional Boot Mode Pin (Pin is bidirectional, pull up or force to zero), to additionally set JTAG only boot mode (to avoid programming problems with some vivado versions, see: AR#00002 - QSPI Programming issues)


Remove 4x5 module

Widget Connector
urlhttps://www.youtube.com/watch?v=uisv2dWbktc

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