Versions Compared
Key
- This line was added.
- This line was removed.
- Formatting was changed.
Page properties | ||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||
Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
|
Custom_table_size_100 |
---|
Page properties | ||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||
Important General Note:
|
Overview
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Zynq PS Design with Linux Example
Refer to http://trenz.org/te0727-info for the current online version of this manual and other available documentation.
Key Features
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Excerpt |
---|
|
Revision History
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Scroll Title | ||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||
|
Release Notes and Know Issues
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Requirements
Software
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Scroll Title | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||
|
Hardware
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||
*used as reference |
Design supports following carriers:
Scroll Title | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||
*used as reference |
Additional HW Requirements:
Scroll Title | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||
*used as reference |
Content
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
Scroll Title | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||
|
Additional Sources
Scroll Title | ||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||
|
Prebuilt
Page properties | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes :
|
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Reference Design is available on:
Design Flow
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Notes :
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
---|
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Boot.bin on QSPI Flash and image.ub and boot.scr on SD.
- Connect USB Power In to get power on module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language bash theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0727 (optional)
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Remove cable from USB Power In
- Copy image.ub and boot.scr on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Important: Do not copy Boot.bin on SD (it is not used; see SD note), only other files.
- Copy init.sh on SD
- location: <project folder>/misc/sd/
- Insert SD-Card in SD-Slot.
- Connect USB Power In to get power on module
SD-Boot mode
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot (fsbl, u-boot) and SD for secondary boot (image.ub, boot.src)
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Insert SD Card with image.ub and boot.src
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
Expand title boot process 1. Zynq Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze,
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C 1 Bus) lsusb (USB check)
Option Features
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- init.sh scripts
System Design - Vivado
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Block Design
Scroll Title | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||
|
PS Interfaces
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
Activated interfaces:
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||
|
Constrains
Basic module constrains
Code Block | ||||
---|---|---|---|---|
| ||||
# # Common BITGEN related settings for TE0727 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] |
Design specific constrain
Code Block | ||||
---|---|---|---|---|
| ||||
# # # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Code Block | ||||
---|---|---|---|---|
| ||||
#set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}] #set_property PACKAGE_PIN H13 [get_ports {HPD_A}] #set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}] #set_property PACKAGE_PIN G14 [get_ports {GLED[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}] #set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}] #set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}] #set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}] #set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}] # #set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}] #set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}] #set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}] #set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}] #set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}] #set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}] #set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}] #set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}] #set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}] # #set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}] #set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}] #set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}] #set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}] #set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}] #set_property PACKAGE_PIN P8 [get_ports {GPIO_tri_io[5]}] #set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}] #set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}] #set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}] #set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}] #set_property PACKAGE_PIN P9 [get_ports {GPIO_tri_io[10]}] #set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}] #set_property PACKAGE_PIN M9 [get_ports {GPIO_tri_io[12]}] #set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}] #set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}] #set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}] #set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}] #set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}] #set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}] #set_property PACKAGE_PIN N9 [get_ports {GPIO_tri_io[19]}] #set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}] #set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}] #set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}] #set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}] #set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}] #set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}] #set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}] #set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}] #set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}] # |
Software Design - Vitis
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For Vitis project creation, follow instructions from:
Application
Page properties | ||||
---|---|---|---|---|
| ||||
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
fsbl
TE modified 2020.2 FSBL
General:
- Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0727
Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Note:
|
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- No changes.
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
Code Block | ||
---|---|---|
| ||
Device Tree
Code Block | ||
---|---|---|
| ||
/include/ "system-conf.dtsi" / { }; &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; partition@0x00000000 { label = "boot"; reg = <0x00000000 0x00500000>; }; partition@0x00500000 { label = "bootenv"; reg = <0x00500000 0x00020000>; }; partition@0x00520000 { label = "kernel"; reg = <0x00520000 0x00a80000>; }; partition@0x00fa0000 { label = "spare"; reg = <0x00fa0000 0x00000000>; }; }; }; &gpio0 { interrupt-controller; #interrupt-cells = <2>; }; /* I2C1 */ &i2c1 { #address-cells = <1>; #size-cells = <0>; i2cmux: i2cmux@70 { compatible = "nxp,pca9540"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; ID_I2C@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; CSI_I2C@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; }; }; /* USB */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { usb-phy = <&usb_phy0>; } ; |
FSBL patch
Must be add manually, see template
Kernel
Start with petalinux-config -c kernel
Changes:
- No changes
Change linux-xlnx_%.bbappend:
Code Block | ||
---|---|---|
| ||
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" SRC_URI += "file://devtool-fragment.cfg" SRC_URI += "file://0001-QSPI-s25fl127_8-2020_2.patch" |
- Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y
- CONFIG_util-linux-mount=y
- CONFIG_util-linux-umount=y
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
Additional Software
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Page properties | ||||
---|---|---|---|---|
| ||||
Note: |
No additional software is needed.
App. A: Change History and Legal Notices
Scroll Ignore | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Legal Notices
Include Page | ||||
---|---|---|---|---|
|
Scroll Only | ||
---|---|---|
|
Scroll pdf ignore | ||||||
---|---|---|---|---|---|---|
|