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Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board" Date | Version | Changes | Author |
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| 2022-02-28 | 2.0 | - add yocto to
- Overview → Key Features
- Overview → Requirements
- Design Flow
- Launch
- add section 'Software Design - Yocto'
| TD | 2021-06-15 | 1.2 | - table of content view
- template history
- placed a horizontal separation line under each chapter heading
- replaced <design name> by <project folder>
- changed title-alignment for tables from left to center
- update 19.x to 20.x
| JH,TD | 2020-11-24 | 1.1 | - add fix table of content
- add table size as macro
| JH | -- | 1.0 | -- | -- |
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Important General Note: Export PDF to download, if quartus revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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Refer to http://trenz.org/te0xyztei0022-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - Add basic key futures, which can be tested with the design
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- Quartus 20.4 Pro1.1 Lite
- Yocto
- NIOS IISD
- UART
- ETH
- USB
- I2C
- QSPI flashHDMI
- DDR3 memory
- User LED
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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anchor | Table_DRH |
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title-alignment | center |
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title | Design Revision History |
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repeatTableHeaders | default |
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sortEnabled | false |
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Date | Quartus | Project Built | Authors | Description |
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20214 ProTEI0006-test_board_noprebuilt-quartus_20. | 4020210615152704TEI0006TEI0022-test_board-quartus_20. | 402021061515272920220203153430.zip | Thomas Dück | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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anchor | Table_KI |
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title-alignment | center |
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title | Known Issues |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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anchor | Table_SW |
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title-alignment | center |
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title | Software |
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orientation | portrait |
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Software | Version | Note |
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Quartus Prime | Pro4NIOS II SBT for Eclipse | --- | Intel SoC FPGA EDS Standard Edition | 20.1 | needed | optionalSI ClockBuilder Pro | ---optional |
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Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
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Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
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title-alignment | center |
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title | Hardware Modules |
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Module Model | Board Part Short Name | Yocto Machine Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TEI0022-03* | A5_C8_2GB | tei0022-a5-c8-2gb | REV03 | 1GB | 32MB | -- | -- | -- |
*used as reference |
Design supports following carriers:
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title-alignment | center |
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title | Hardware Carrier |
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orientation | portrait |
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*used as reference |
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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Additional Hardware | Notes |
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USB cable for JTAG/UART | Check Carrier Board and Programmer for correct type | Monitor | tested with DELL U2412M | Keyboard | -- | Mouse | -- | HDMI cable | -- |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - Intel devices
Design Sources
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Type | Location | Notes |
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Quartus | <project folder>/source_files/quartus <project folder>/source_files/<Board Part Short Name>/quartus | Quartus project will be generated by TE Scripts optional, source files for specific assembly variants | Software | <project folder>/source_files/software <project folder>/source_files/<Board Part Short Name>/software | Additional software will be generated by TE Scripts optional, source files for specific assembly variants | Yocto | <project folder>/source_files/os/yocto | Yocto BSP layer template for linux |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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title-alignment | center |
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File | File-Extension | Description |
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SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware | SRAM Object File | *.sof | Ram configuration file | Programmer Object File | *.pof | FPGA configuration file | JTAG Indirect Configuration file | *.jic | Flash configuration file | Raw binary file | *.rbf | FPGA configuration file | Diverse Reports | --- | Report files in different formats | Software-Application-File | *.elf | Software application for NIOS II processor system |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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File | File-Extension | Description |
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SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware | SRAM Object File | *.sof | Ram configuration fileJTAG indirect configuration file | *.jic | Flash configuration file | Raw binary file | *.rbf | FPGA configuration file | Diverse Reports | --- | Report files in different formats | Software-Application-FileYocto linux image | *.elfwic | Software application for NIOS II processor systemLinux image for SD card |
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Download
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
- Open create_project_win.cmd/create_project_linux.sh:
'Create Project' GUI example - Select Board in "Board selection"
- Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
- Create and configure your Yocto Linux project, see Yocto KICKstart
- Copy the generated meta-<module> folder from <project name>/os/yocto/meta-<module> to the path/to/yocto/poky/ directory
- Follow the steps from Yocto KICKstart#Create a project for an Intel FPGA device without running the 'bitbake' command
Add the generated bsp layer meta-<machine> to path/to/yocto/poky/build/conf/bblayers.conf with:
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bitbake-layers add-layer ../meta-<module>tei0022 |
Info |
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Note: The generated meta-<module> tei0022 layer depends on the meta-altera layer (for more information see: Yocto KICKstart#Used source files), so you need to add both bsp layers to bblayers.conf |
Redefine the variable MACHINE with '<module>tei0022-<Board-Part-Short-Name>' in path/to//yocto/poky/build/conf/local.conf. The correct MACHINE name can be found in the #Hardware table.
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sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf
echo -e '\nMACHINE = "<module>tei0022-<Board-Part-Short-Name>"' >> conf/local.conf |
Build the image with following command (the image recipes are located in meta-<module>/recipes-images/yocto/):
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theme | Midnight |
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linenumbers | true |
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bitbake <module>tei0022-image-minimal |
Launch
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
SD-Boot mode
- Follow the steps described in Yocto KICKstart#Copy image to SD card to copy the generated linux image to the SD card.
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier module TRM .for correct settings
- Insert SD-Card in SD-Slot.
QSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd/create_project_linux.sh
- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this example.
Usage
Not used on this example.
JTAG
Not used on this example.
Usage
- Prepare HW like Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power Power on PCB
UART
- Open Serial Console (e.g. PuTTY)
select COM Port
Info |
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Win OS: see device manager Linux OS: see dmesg | grep tty (UART is *USB1) |
- Speed: 115200
- Press reset buttonConsole output depends on used Software project, see Software Design - SDK#Application
- Linux Console:
Login data:
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Note: Wait until Linux boot finished |
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theme | Midnight |
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linenumbers | true |
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yocto loginUsername: root
Password: root |
info |
Note: Wait until Linux boot finished |
You can use Linux shell now.
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theme | Midnight |
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linenumbers | true |
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i2cdetect -y -r 1 (check I2C 1 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
- ...
System Design - Quartus
Block Design
The block designs may differ depending on the assembly variant.
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Project |
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>>Project<< Image Added |
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Platform Desginer |
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>>Platform Designer<< Image Added |
HPS Interfaces
Activated interfaces:
EMAC0EMAC1GPIO0GPIO1GPIO2QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB0 | -- |
USB1 | -- |
CAN0 | -- |
CAN1 | -- |
Software Design - SDK
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Application
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---------------------------------------------------------- General Example: hello_tei0006Hello TEI0006 is a Hello World example as endless loop instead of one console output. |
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
...
Software Design - Yocto
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For Yocto installation and project creation, follow instructions from:
U-Boot
Start with Create a custom BSP layer for Intel SoC or FPGA#Configure u-boot
File location: meta-<module>/recipes-bsp/u-boot/
Changes:
Device Tree
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#device tree
/ {
};
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Kernel
Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernelGPIO35 | connected to ETH PHY_INT pin |
GPIO42 | connected to USB_RST pin |
GPIO43 | connected to ETH_RST pin |
GPIO48 | connected to CPU_GPIO_0 pin |
GPIO53 | connected to LED_HPS_1 pin |
GPIO54 | connected to LED_HPS_2 pin |
GPIO55 | connected to CPU_GPIO_3 pin |
GPIO56 | connected to CPU_GPIO_2 pin |
GPIO57 | connected to USER_BTN_HPS pin |
GPIO58 | connected to CPU_GPIO_1 pin |
GPIO61 | connected to CPU_GPIO_4 pin |
Software Design - Yocto
For Yocto installation and project creation, follow instructions from:
U-Boot
Start with Create a custom BSP layer for Intel SoC or FPGA#Configure u-boot
File location: meta-tei0022/recipes-bsp/u-boot/
Changes:
Device Tree
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language | js |
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title | Excerpts from test_board/os/yocto/meta-tei0022/recipes-bsp/u-boot/files/tei0022_<Board_Part_Short_Name>/dts/tei0022_<Board_Part_Short_Name>.dts |
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#include "socfpga_cyclone5.dtsi"
#include "dt-bindings/interrupt-controller/irq.h"
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
axi_dma_clk: axi_dma_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "axi_dma_clock";
};
sys_clk: sys_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
clock-output-names = "sys_clock";
};
hdmi_pll: hdmi_pll {
compatible = "altr,altera_iopll-18.1";
#clock-cells = <1>;
hdmi_pll_outclk0: hdmi_pll_outclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
clock-output-names = "hdmi_pll-outclk0";
};
};
vdd: regulator-vdd {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vdd_3_3: regulator-vdd {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vref: regulator-vref {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
soc {
i2c1: i2c@ffc05000 {
status = "okay";
speed-mode = <0>;
#address-cells = <1>;
#size-cells = <0>;
adv7511: adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39>, <0x3f>;
reg-names = "primary", "edid";
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "right";
adi,clock-delay = <(0)>;
avdd-supply = <&vdd>;
dvdd-supply = <&vdd>;
pvdd-supply = <&vdd>;
dvdd-3v-supply = <&vdd_3_3>;
bgvdd-supply = <&vdd>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&axi_hdmi_out>;
};
};
port@1 {
reg = <1>;
};
};
};
};
sys_hps_bridges: bridge@ff200000 {
compatible = "simple-bus";
reg = <0xff200000 0x00200000>;
reg-names = "axi_h2f_lw";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000001 0x00001000 0xff201000 0x00000010>,
<0x00000001 0x00001010 0xff201010 0x00000010>,
<0x00000001 0x00001020 0xff201020 0x00000008>,
<0x00000001 0x00001030 0xff201030 0x00000008>,
<0x00000001 0x00010000 0xff210000 0x00000800>,
<0x00000001 0x00020000 0xff220000 0x00010000>;
jtag_uart: jtag-uart@100001030 {
compatible = "altr,juart-1.0";
reg = <0x00000001 0x000001030 0x00000008>;
interrupts = <0 40 4>;
};
sysid: sysid@100001020 {
compatible = "altr,sysid-1.0";
reg = <0x00000001 0x00001020 0x00000008>;
};
fpga_sw: fpga-sw@100001000 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x00001000 0x00000010>;
interrupts = <0 41 1>;
altr,gpio-bank-width = <2>;
#gpio-cells = <2>;
gpio-controller;
interrupt-cells = <1>;
interrupt-controller;
altr,interrupt-type = <IRQ_TYPE_EDGE_BOTH>;
};
fpga_led: fpga-led@100001010 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x00001010 0x00000010>;
altr,gpio-bank-width = <2>;
#gpio-cells = <2>;
gpio-controller;
};
leds {
compatible = "gpio-leds";
fpgaled0 {
label = "fpga_led0";
gpios = <&fpga_led 0 1>;
};
fpgaled1 {
label = "fpga_led1";
gpios = <&fpga_led 1 1>;
};
};
hdmi_axi_dmac: axi-dmac@100010000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x00000001 0x00010000 0x00000800>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 42 4>;
clocks = <&axi_dma_clk 0>;
status = "okay";
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <1>;
};
};
};
hdmi_axi_tx: axi-hdmi-tx@100020000 {
compatible = "adi,axi-hdmi-tx-1.00.a";
reg = <0x00000001 0x00020000 0x10000>;
dmas = <&hdmi_axi_dmac 0>;
dma-names = "video";
clocks = <&hdmi_pll_outclk0 0>;
status = "okay";
port {
axi_hdmi_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
};
};
&gmac1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-mode = "rgmii";
ethernet-phy@1 {
reg = <1>;
adi,rx-internal-delay-ps = <2000>;
adi,tx-internal-delay-ps = <2000>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
eeprom: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
|
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language | js |
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title | Excerpts from test_board/os/yocto/meta-tei0022/recipes-kernel/linux/files/dts/tei0022_<Board_Part_Short_Name>.dts |
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|
#include "socfpga_cyclone5.dtsi"
#include "dt-bindings/interrupt-controller/irq.h"
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
axi_dma_clk: axi_dma_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-output-names = "axi_dma_clock";
};
sys_clk: sys_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
clock-output-names = "sys_clock";
};
hdmi_pll: hdmi_pll {
compatible = "altr,altera_iopll-18.1";
#clock-cells = <1>;
hdmi_pll_outclk0: hdmi_pll_outclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
clock-output-names = "hdmi_pll-outclk0";
};
};
vdd: regulator-vdd {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vdd_3_3: regulator-vdd {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vref: regulator-vref {
compatible = "regulator-fixed";
regulator-name = "fixed-supply";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
soc {
i2c1: i2c@ffc05000 {
status = "okay";
speed-mode = <0>;
#address-cells = <1>;
#size-cells = <0>;
adv7511: adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39>, <0x3f>;
reg-names = "primary", "edid";
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "right";
adi,clock-delay = <(0)>;
avdd-supply = <&vdd>;
dvdd-supply = <&vdd>;
pvdd-supply = <&vdd>;
dvdd-3v-supply = <&vdd_3_3>;
bgvdd-supply = <&vdd>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&axi_hdmi_out>;
};
};
port@1 {
reg = <1>;
};
};
};
};
sys_hps_bridges: bridge@ff200000 {
compatible = "simple-bus";
reg = <0xff200000 0x00200000>;
reg-names = "axi_h2f_lw";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000001 0x00001000 0xff201000 0x00000010>,
<0x00000001 0x00001010 0xff201010 0x00000010>,
<0x00000001 0x00001020 0xff201020 0x00000008>,
<0x00000001 0x00001030 0xff201030 0x00000008>,
<0x00000001 0x00010000 0xff210000 0x00000800>,
<0x00000001 0x00020000 0xff220000 0x00010000>;
fpga_sw: fpga-sw@100001000 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x00001000 0x00000010>;
interrupts = <0 41 1>;
altr,gpio-bank-width = <2>;
#gpio-cells = <2>;
gpio-controller;
interrupt-cells = <1>;
interrupt-controller;
altr,interrupt-type = <IRQ_TYPE_EDGE_BOTH>;
};
fpga_led: fpga-led@100001010 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x00001010 0x00000010>;
altr,gpio-bank-width = <2>;
#gpio-cells = <2>;
gpio-controller;
};
leds {
compatible = "gpio-leds";
fpgaled0 {
label = "fpga_led0";
gpios = <&fpga_led 0 1>;
};
fpgaled1 {
label = "fpga_led1";
gpios = <&fpga_led 1 1>;
};
};
sysid: sysid@100001020 {
compatible = "altr,sysid-1.0";
reg = <0x00000001 0x00001020 0x00000008>;
};
jtag_uart: jtag-uart@100001030 {
compatible = "altr,juart-1.0";
reg = <0x00000001 0x000001030 0x00000008>;
interrupts = <0 40 4>;
};
hdmi_axi_dmac: axi-dmac@100010000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x00000001 0x00010000 0x00000800>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 42 4>;
clocks = <&axi_dma_clk 0>;
status = "okay";
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <1>;
};
};
};
hdmi_axi_tx: axi-hdmi-tx@100020000 {
compatible = "adi,axi-hdmi-tx-1.00.a";
reg = <0x00000001 0x00020000 0x10000>;
dmas = <&hdmi_axi_dmac 0>;
dma-names = "video";
clocks = <&hdmi_pll_outclk0 0>;
status = "okay";
port {
axi_hdmi_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
};
};
&gmac1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-mode = "rgmii-id";
ethernet-phy@1 {
reg = <1>;
adi,rx-internal-delay-ps = <2000>;
adi,tx-internal-delay-ps = <2000>;
};
};
|
Kernel
Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernel
File location: meta-<module>/recipes-kernel/linux/
Changes:
- for hdmi output
set TE boot logo
CONFIG_LOGO=y
CONFIG_LOGO_TRENZELECTRONICS_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
config ethernet phy
CONFIG_PHYLIB=y
CONFIG_ADIN_PHY=y
set debug settings
File location: meta-<module>/recipes-kernel/linux/
Changes:
Images
Image recipe for minimal console image
File location: meta-<module>/recipes-images/yocto/
Added packages/recipes:
No packages/recipes.tei0022-rbf
ethtool
i2c-tools
net-tools
usbutils
Rootfs
Optional it's possible to create a debian or ubuntu rootfs with/without desktop environment for this board. For more information and instructions see: Create debian/ubuntu rootfs - Intel devices
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Legal Notices
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