Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic AM0010 module is an industrial(???) grade module based on Xilinx.

Refer to http://trenz.org/AM0010-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC/FPGA
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 ¹⁾
- Engine: CG / EG / EV ¹⁾
- Speedgrade: -1 / -2 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: SFVC784
RAM/Storage
- 4 GByte DDR4 SDRAM with ECC ²⁾
- 8 GByte e.MMC ³⁾
- 64 MByte HyperFlash ⁴⁾
- 2 x 64 MByte Serial Flash ⁵⁾
- EEPROM with MAC address
On Board
- Gigabit Ethernet Transceiver
- USB Transceiver (USB3320 or USB3340 ⁶⁾)
- OPTIGA Trust M
- CryptoAuthentication
- Oscillator
- Analog Multiplexer
Interface
- 2 x B2B Connector (ADM6)
Power
- 5 V ... 12 V power supply via B2B Connector needed.
Dimension
- 5.6 mm x 4 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 32 GByte are possible with a maxmum bandwidth of 2400 MBit/s.
³⁾ Up to 64 GByte are possible.
⁴⁾ Smaller values are possible.
⁵⁾ Up to 2 x 256 MByte are possible.
⁶⁾ USB 2.0 devices are possible with USB33040 but USB 3.X devices needs additional customer engagement.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	AM0010 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	AM0010_OV_BD
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	691
revision	47

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Image Added

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	AM0010 main components

Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	720
revision	3

Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Image Added

FPGA, U1
DDR4, U2, U3, U9, U12, U14
eMMC, U17
Serial Quad SPI Flash, U6, U7
Connector, J5, J6
Ethernet Transceiver, U8
HyperFlash, U16
EEPROM, U15
OPTIGA Trust M, U27
CryptoAuthentication, U24
USB Transceiver, U10
Oscillator, U13, U14, U30, U31, U32
Analog Multiplexer, U38
Power Supply, U5, U11, U18, U19, U20, U21, U22, U23, U28

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
DDR4 SDRAM	not programmed
eMMC	not programmed
Quad SPI Flash	EEPROM	System Controller CPLD	DDR4 SDRAM	eMMC	Programmable Clock Generator

Configuration Signals

not programmed
HyperFlash	not programmed
EEPROM	not programmed besides factory programmed MAC address

Signals, Interfaces and Pins

Overview of Boot Mode, Reset, Enables.

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designtor List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

B2B/

Scroll Title

anchor	Table_OVSIP_CNTRLC
title-alignment	center
title	Controller signal.Board Connectors

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Name

Connector Type

Direction

Designator

Description

Interface

Boot Mode

IO CNT

Enable

Notes

Reset

B2B

JTAGSEL

J5

PGOOD...

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown

HP	104 SE / 48 DIFF
B2B	J5	MGT PL	4 x MGT (RX/TX)
B2B	J5	MGT PL	2 x MGT CLK
B2B	J5	HD	24 SE / 12 DIFF
B2B	J6	HP	52 SE / 24 DIFF
B2B	J6	MGT PS	4 x MGT (RX/TX)
B2B	J6	MGT PS	2 x MGT CLK
B2B	J6	HD	24 SE / 12 DIFF
B2B	J6	MIO	2 x I2C
B2B	J6	MIO	2 x UART
B2B	J6	MIO	2 x PERST
B2B	J6	MIO	SDIO
B2B	J6	MIO	JTAG
B2B	J6	MIO	4 x GPIO
B2B	J6	ETH
B2B	J6	USB

Test Points

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B2B SoC/FPGA IOs

B2B JTAG Interface

B2B ETH Interface

B2B USB Interface

SD Card Connector

SMA Connector

MIO

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Note

title	Note

MIO section only for SoC devices with dedicated MIO, otherwhise remove this section

MIO Pins

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Only for SoC Modules(Xilinx MIO, for Intel and MicroChip SoC please change MIO to syntax of the manufacturer). you must fill the table below with group of MIOs Test Point which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

MIO Pins are only for SoC like Zynq, U+Zynq and Versal, for other FPGA modules remove this chapter

Example:

indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point

Signal

MIO Pin

Connected to

B2B

Notes

MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2

QSPI

Test Points

10

PWR_PL_OK

J2-120

TP10

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal

B2B

Connected to	Notes

10

TP1

PWR

PROG_

PL_OK

B#

J2-120

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

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1

sortEnabled

false

cellHighlighting

true

Test Point

Signal

Connected to

Notes

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

pulled-up to V_IO_CFG
TP2	VTT
TP3	VTT
TP4	VREFA
TP5	VREFA
TP6	0.85V
TP7	0.85V
TP8	DDR_1V2
TP9	DDR_1V2
TP10	MGTAVCC
TP11	MGTAVCC
TP12	DDR_2V5
TP13	DDR_2V5
TP14	PL_VCU_0V9
TP15	PL_VCU_0V9
TP16	1.8V
TP17	1.8V
TP18	3.3V_SEQ
TP19	3.3V_SEQ
TP20	3.3V
TP21	3.3V

Custom_table_size_100

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Power and Power-On Sequence

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id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

DDR4 SDRAM	U2, U3, U9, U12, U14	FPGA - PS
eMMC	U17	FPGA - PS
Quad SPI Flash	U6, U7	FPGA - PS
Ethernet Transceiver	U8	FPGA - PS
HyperFlash	U16	FPGA - PL
EEPROM	U15	FPGA - PS
OPTIGA Trust M	U27	FPGA - PS
CryptoAuthentication	U24	FPGA - PS
USB Transceiver	U10	FPGA - PS
Oscillator	U13	FPGA - PS
Oscillator	U14	FPGA - PS
Oscillator	U30	ETH PHY
Oscillator	U31	USB PHY
Oscillator	U32	FPGA
Analog Multiplexer	U38	FPGA

Page properties

hidden	true
id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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hidden	true
id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Scroll Title

anchor	Table_PWR_PC
title-alignment	center
title	Power Consumption

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Input PinTypical CurrentVINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title

anchor	Figure_PWR_PD
title-alignment	center
title	Power DistributionController signal.

scroll-

ignore

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Scroll Only
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Power-On Sequence

Scroll Title

anchor	Figure_PWR_PS
title-alignment	center
title	Power Sequency

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

tablelayout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin	Signal Name	Direction	Description
J6.A59	V_BAT	C2M	Input voltage for VCC_PSBATT
J6.B58	RST_M2C#	M2C	Module reset for peripheral reset
J6.C53	DONE	M2C	FPGA PS_DONE-signal
J6.C54	MODE0	C2M	Boot mode selection
J6.C55	MODE1	C2M	Boot mode selection
J6.C56	MODE2	C2M	Boot mode selection
J6.C57	MODE3	C2M	Boot mode selection
J6.C58	PS_SRST#	C2M	FPGA system reset
J6.C59	PS_POR#	bidirectional	Power-on-reset status
J6.D56	DX_P	C2M	Temperature sensing diode pin
J6.D57	DX_N	C2M	Temperature sensing diode pin
J6.D58	PWR_EN	C2M	Power Enable (Do not tie "PWR_EN" to VDD directly. This signal could be tied to GND within this module.)
J6.D59	PWR_GOOD	M2C	Power good status

Legend:

C2M: Carrier to Module

M2C: Module to Carrier

Power and Power-On Sequence

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id	Comments

Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

Voltage Monitor Circuit

Scroll Title

anchor	Figure_PWR_VMC
title-alignment	center
title	Voltage Monitor Circuit

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Power Rails

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

Bank Voltages

Scroll Title

anchor	Table_PWR_BV
title-alignment	center
title	Zynq SoC bank voltages.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

Bank

Schematic Name

Voltage

NotesBoard to Board Connectors

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Page properties
hidden true
id Comments
Include Page
PD:6 x 6 SoM LSHM B2B Connectors PD:6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

title
anchor	Table_PWR_PR

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	PS absolute maximum ratingsModule power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Symbols

Description

Min

Max

Unit

V

°C

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Power Rail Name/ Schematic Name	Connector.Pin	Direction
V_MOD1	J5.A7	C2M
V_MOD1	J5.A15	C2M
V_MOD1	J5.A47	C2M
V_MOD1	J5.A55	C2M
V_MOD1	J5.B5	C2M
V_MOD1	J5.B11	C2M
V_MOD1	J5.B17	C2M
V_MOD1	J5.B45	C2M
V_MOD1	J5.B51	C2M
V_MOD1	J5.B57	C2M
1.8V	J5.C7	M2C
1.8V	J5.C15	M2C
V_IO_W01	J5.D3	C2M
V_IO_W01	J5.D17	C2M
V_IO_W3	J5.D40	C2M
V_IO_W45	J5.D43	C2M
V_IO_W45	J5.D57	C2M
V_IO_X01	J6.A3	C2M
V_IO_X01	J6.A17	C2M
V_BAT	J6.A59	C2M
1.8V	J6.B7	M2C
1.8V	J6.B15	M2C
V_IO_X3	J6.B35	C2M
3.3V	J6.B59	M2C
V_MOD1	J6.C5	C2M
V_MOD1	J6.C11	C2M
V_MOD1	J6.C17	C2M
V_IO_CFG	J6.C52	C2M
V_MOD1	J6.D7	C2M
V_MOD1	J6.D15	C2M

Board to Board Connectors

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id	Comments

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=139253650&moved=true
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=139253650&moved=true

Technical Specifications

Absolute Maximum Ratings

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	AM0010 absolute maximum ratings

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
V_MOD1	Main input power supply	-0.3	18	V
V_IO_W01	HP FPGA Bank 65 voltage	-0.500	2.000	V
V_IO_W3	HD FPGA Bank 24 voltage	-0.500	3.400	V
V_IO_W45	HP FPGA Bank 64 voltage	-0.500	2.000	V
V_IO_X01	HP FPGA Bank 66 voltage	-0.500	2.000	V
V_BAT (using LDO)	FPGA Battery Voltage		6	V
V_BAT (using resistor)	FPGA Battery Voltage	-0.500	2.000	V
V_IO_X3	HD FPGA Bank 24 voltage	-0.500	3.400	V
V_IO_CFG	PS FPGA Bank 501 and 503 Voltage	-0.3	3.630	V

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Scroll Title

anchor	Table_TS_ROC
title-alignment	center
title	Recommended operating conditions.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Parameter	Min	Max	Units	Reference Document
V_MOD1	4.5	16	V	See TPS54A24 and FS1406 datasheets.
V_IO_W01	0.950	1.900	V	See FPGA datasheet.
V_IO_W3	1.140	3.400	V	See FPGA datasheet.
V_IO_W45	0.950	1.900	V	See FPGA datasheet.
V_IO_X01	0.950	1.900	V	See FPGA datasheet.
V_BAT (using LDO)	2.0	5.5	V	See AP7354D datasheet.
V_BAT (using resistor)	1.200	1.89	V	See FPGA datasheet.
V_IO_X3	1.140	3.400	V	See FPGA datasheet.
V_IO_CFG	1.710	3.465	V	See FPGA

Scroll Title

anchor	Table_TS_ROC
title-alignment	center
title	Recommended operating conditions.

Scroll Table Layout

orientation

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See ????

Parameter	Min	Max	Units	Reference Document
V	See ???? datasheets.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	°C	datasheet.

Physical Dimensions

Module size: ?? 56.4 mm × ?? 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 5 mm.

PCB thickness: ?? 2 mm.

Page properties

hidden	true
id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_TS_PD
title-alignment	center
title	Physical Dimension

Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.are only linked.

draw.io Diagram

border	true

diagramName	Figure_TS_PD
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	626
revision	2

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Image Added

Currently Offered Variants

Page properties

hidden	true
id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Scroll Title

anchor	Table_VCP_SO
title-alignment	center
title	Trenz Electronic Shop Overview

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Trenz shop TEXXXX AM0010 overview page
English page	German page

Revision History

Hardware Revision History

Page properties

hidden	true
id	Comments

Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Scroll Title

anchor	Figure_RV_HRN
title-alignment	center
title	Board hardware revision number.
	center
title	Board hardware revision number.

Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

draw.io Diagram

border	true

diagramName	Figure_RV_HRN
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	223
revision	1

Image Added

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

Scroll Title

anchor	Table_RH_HRH
title-alignment	center
title	Hardware Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Revision	Changes	Documentation Link
-	01	First Production Release

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_RH_DCH
title-alignment	center
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

<add TRM change list here>

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

--Initial Document

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Scroll Only

HTML
<style> .wiki-content .columnLayout .cell.aside { width: 0%; }</style>

Scroll pdf ignore

Custom_fix_page_content

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 10

New Version 11

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Signals, Interfaces and Pins

Test Points

B2B SoC/FPGA IOs

B2B JTAG Interface

B2B ETH Interface

B2B USB Interface

SD Card Connector

SMA Connector

MIO

MIO Pins

Test Points

Custom_table_size_100

On-board Peripherals

Power and Power-On Sequence

Configuration and System Control Signals

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power and Power-On Sequence

Power Rails

Voltage Monitor Circuit

Power Rails

Bank Voltages

This section is optional and only for modules.use "include page" macro and link to the general B2B connector page of the module series,For example: 6 x 6 SoM LSHM B2B Connectors Page propertieshiddentrueidComments Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Page properties
hidden true
id Comments
Include Page
PD:6 x 6 SoM LSHM B2B Connectors PD:6 x 6 SoM LSHM B2B Connectors