Page History

Important General Note:

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Figure template (note: inner scroll ignore/only only with drawIO object):

Overview

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Overview

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Revision History

• initial release

Release Notes and Know Issues

Do not use HW Manager connection, or if debugging is necessary:

1. Boot linux with usb terminal
2. From the terminal: root root mount ifconfig eth0
3. Open two new SSH terminals via ethernet: root root , run user application ...
4. Exit and close the usb terminal

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - Xilinx AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

• TE0808 "StarterKit" Reference Design

Design Flow

See also:

• Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"
3. Create Project (project and follow instruction instructions of the product selection guide), settings file will be configured automatically during this process.
   (

   • optional for manual changes

   )

   • : Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see

   TE

   • also Vivado Board Part

   Files

   • Flow

            

   • Important: Use Board Part Files, which ends with *_tebf0808

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

7. Vivado GUI is the same, except file export to prebuilt folder.

   
   

8. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the

   Copy PetaLinux build image files to prebuilt folder

   • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
     

     Info
     "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

     Page properties

     hidden	true
     id	Comments

     This step depends on Xilinx Device/Hardware

     for Zynq-7000 series

     copy u-boot.elf, image.ub and boot.scr from

     "<plnx-proj-root>/images/linux"directory

9. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

10. Generate Programming Files with Vitis (recommended)
    
    1. Copy PetaLinux build image files to prebuilt folder
    for ZynqMP
    1. • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
         

    for ...

    • ...

    1. Generate Programming Files

    with Vitis

    1. Code Block
       language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
       TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

       
       

       Note
       TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

       
       

11. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Get prebuilt boot binaries

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder

Select create and open delivery binary folder

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0808 (optional)

   Note
   To program with Vitis/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

   Copy image.ub and boot.scr on SD or USB
   use files from

   1. "<project folder>\_binaries_<Article Name>

   \

   1. " with subfolder "boot_

   linux" from generated binary folder,see: Get prebuilt boot binariesor use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"

   1. <app name>" for different applications will be generated

      
      

QSPI-Boot mode

Option for Boot.bin on QSPI Flash.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp hello_te0808

   
   

3. Set Boot Mode to QSPI-Boot and insert SD or USB.
   
   • Depends on Carrier, see carrier TRM.
   • TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

SD-Boot mode

1. Copy image.ub, boot.srcscr and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
5. (Optional with TEBF0808) Connect SATA Disc
6. (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
7. (Optional with TEBF0808) Connect Network Cable

8. Power On PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

     
     

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   # password disabled petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC checki2cdetect -y -r 0 (check I2C 1 Bus) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)

   
   

4. Option Features

   • Webserver to get access to ZynqZynqMP
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado Hardware Manager

• RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
  

  • Set Enable to send Write date over RGPIO interface. 
    • Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
      • Buttons, LEDs, Status...

• Control:
  • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
  • CAN_S
    

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title-alignment center title Block Design
Image RemovedImage Added

PS Interfaces

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

#System Controller IP
  #LED_HD SC0 J3:31
  #LED_XMOD SC17 J3:48 
  #CAN RX SC19 J3:52 B47_L2_P in
  #CAN TX SC18 J3:50 B47_L2_N out 
  #CAN S  SC16 J3:46 B47_L3_N out
set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
set_property PACKAGE_PIN E14 [get_ports BASE_sc15] 
  #CAN S  SC16 J3:46 B47_L3_N out
#HDIO_SC1    K14
#HDIO_SC2    H13
#HDIO_SC3    H14
#HDIO_SC4    F13



#HDIO_SC0    J14
set_property PACKAGE_PIN A13J14 [get_ports BASE_sc16]sc0]
#HDIO_SC5    G13
set_property PACKAGE_PIN B13G13 [get_ports BASE_sc17sc5]
#HDIO_SC6    J15
set_property PACKAGE_PIN A14J15 [get_ports BASE_sc18]sc6]
#HDIO_SC7    K15
set_property PACKAGE_PIN B14K15 [get_ports BASE_sc19sc7]
#HDIO_SC10   A15
set_property IOSTANDARDPACKAGE_PIN LVCMOS18A15 [get_ports BASE_sc0]sc10_io]
#HDIO_SC11   B15
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B15 [get_ports BASE_sc5sc11]
#HDIO_SC12   C13
set_property IOSTANDARDPACKAGE_PIN LVCMOS18C13 [get_ports BASE_sc6]sc12]
#HDIO_SC13   C14
set_property IOSTANDARDPACKAGE_PIN LVCMOS18C14 [get_ports BASE_sc7sc13]
#HDIO_SC14   E13
set_property IOSTANDARDPACKAGE_PIN LVCMOS18E13 [get_ports BASE_sc10_io]sc14]
#HDIO_SC15   E14
set_property IOSTANDARDPACKAGE_PIN LVCMOS18E14 [get_ports BASE_sc11sc15]
#HDIO_SC16   A13
set_property IOSTANDARDPACKAGE_PIN LVCMOS18A13 [get_ports BASE_sc12]sc16]
#HDIO_SC17   B13
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B13 [get_ports BASE_sc13sc17]
#HDIO_SC18   A14
set_property IOSTANDARDPACKAGE_PIN LVCMOS18A14 [get_ports BASE_sc14]sc18]
#HDIO_SC19   B14
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B14 [get_ports BASE_sc15sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19sc7]

# PLL
#setset_property PACKAGE_PINIOSTANDARD AH6LVCMOS18 [get_ports {si570BASE_clk_p[0]}sc10_io]
#setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_p[0]}BASE_sc11]
#setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_n[0]}]
# Clocks
#setBASE_sc12]
set_property PACKAGE_PINIOSTANDARD J8LVCMOS18 [get_ports {B229_CLK1_clk_p[0]}BASE_sc13]
#setset_property PACKAGE_PINIOSTANDARD F25LVCMOS18 [get_ports {B128_CLK0_clk_p[0]}]
# SFP 
#setBASE_sc14]
set_property PACKAGE_PINIOSTANDARD G8LVCMOS18 [get_ports {B230_CLK0_clk_p}]
# B230_RX3_P
#setBASE_sc15]
set_property PACKAGE_PINIOSTANDARD A4LVCMOS18 [get_ports {SFP1BASE_rxp}sc16]
# B230_TX3_P
#set_property PACKAGE_PIN A8set_property IOSTANDARD LVCMOS18 [get_ports {SFP1BASE_txp}sc17]
# B230_RX2_P
#set_property PACKAGE_PIN B2set_property IOSTANDARD LVCMOS18 [get_ports {SFP2BASE_rxp}sc18]
# B230_TX2_P
#setset_property PACKAGE_PINIOSTANDARD B6LVCMOS18 [get_ports {SFP2BASE_txp}sc19]


# Audio Codec
#LRCLK        		  J3:49 B47_L9_N
#BCLK         		   J3:51 B47_L9_P
#DAC_SDATA  	  J3:53 B47_L7_N
#ADC_SDATA  	  J3:55 B47_L7_P

#LRCLK G14
set_property PACKAGE_PIN G14 [get_ports LRCLKI2S_lrclk ]
#BCLK G15
set_property PACKAGE_PIN G15 [get_ports BCLKI2S_bclk ]
#DAC_SDATA E15
set_property PACKAGE_PIN E15 [get_ports DACI2S_sdin ]
#ADC_SDATA ]F15
set_property PACKAGE_PIN F15 [get_ports ADCI2S_SDATAsdout ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLKI2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports DACI2S_SDATAsdin ]
set_property IOSTANDARD LVCMOS18 [get_ports ADCI2S_SDATAsdout ]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

For Vitis project creation, follow instructions from:

Vitis

Application

zynqmp_fsbl

TE modified 20202023.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5345 Configuration
  • OTG+PCIe Reset over MIO
  • I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisationEEPROM MAC

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux