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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Table template:
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Table of contents
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Overview
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TEC0330 SI5338 Configuration, DDR Configuration and PCIe Core Example Design.
Refer to http://trenz.org/tec0330-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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title | Design Revision History |
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- initial release
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title | Known Issues |
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Disable ECC:
- for Block Design MIG with AXI Interface, create 64Bit MIG
- for RTL MIG with Native Interface, disable ECC on MIG configuration and use 72Bit for Data
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
- list of software which was used to generate the design
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- DDR configured for AW24P7228BLK0M (8GB)
Design supports following carriers:
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- TE0790 with TE0791 for CPLD or FPGA
- Xilinx compatible JTAG programmer for FPGA
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- for example:
- AW24P7228BLK0M (max. 8GB)
Content
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Additional HW Requirements:
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title | Additional Hardware |
- content of the zip file
For general structure and of the reference design, see Project Delivery - Xilinx devices
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Prebuilt
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDK
- Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
(optional) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
Note: See SDK Projects - (optional ) Copy "prebuilt\software\<short dir>\srec_spi_bootloader.elf" into "\firmware\microblaze_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))
- (optional ) for SI5338 reprogramming with MCS:
- Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
- New Application with Project Name "SCU" and Processor "microblaze_mcs_0_microblaze_I", select TE Application "SCU-Firmware"
- Create elf file
- Copy "workspace\sdk\SCU\<release or debug>\SCU.elf" into "\firmware\microblaze_mcs_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))
- Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
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