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Impact: None. I2C bus has additional device.
#12 Change SI5338A-B-GM
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firmware.
- New CBP version (4.6) is used which leads to MultiSynth parameter changes.
- Enable optional FPGA Fabric clock CLK0 100 MHz with LVDS.
- Enable clock CLK1 50 MHz with two single ended (Port A and B) CMOS in phase clocks instead of one (Port A) used for ETH PHY syncronisation.
Type: Schematic Change
Reason: Unify settings.
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