Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Perihery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
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Scroll Only
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Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic TE0xxx-xx ... TE0817 is an industrial /extended grade ... module ... based on Xilinx/Intel...grade MPSoC SOM integrating a Xilinx Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/tec0850te0817-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt
SoC/FPGA Device: ZU4 / ZU5 / ZU7 ¹⁾ Engine: CG / EG / EV ¹⁾ Speedgrade: -1 / -2 / -3 ¹⁾ Temperature Range: Extended / Industrial ¹⁾ Package: FBVB900... RAM/Storage 4 GByte DDR4 SDRAM ²⁾ 2 x 64 MByte Serial Flash ³⁾ EEPROM with MAC address... On Board ...Oscillator Interface ... Power ... Dimension ... Notes ...

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TExxxx block diagram

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- 4 x B2B Connector (ADM6)
  - up to 204 PL IO
    - HP: 156
    - HD: 48
  - up to 65 PS MIO
  - 4 GTR
  - 16 GTH
  - I2C, JTAG
Power
- 3.3 V power supply via B2B Connector needed ⁴⁾.
Dimension
- 76 mm x 52 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.
⁴⁾ Dependant on the assembly option a higher input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0813 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	TE0817_OV_BD
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	641
revision	3

Scroll Only
Image Added

Main Components

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Notes :

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TExxxx TE0813 main components

Scroll Ignore
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Scroll Only
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...
...
...

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	1342
revision	1

Scroll Only
Image Added

SoC, U1
DDR4, U2, U3, U9, U12
Quad SPI Flash, U7, U17
Connector, JM1, JM2, JM3, JM4
EEPROM, U28
Clock Generator, U5
Oscillator, U6, U32
Power Supply, U4, U8, U10, U11, U13 ... U16, U18 ... U24, U26, U27, U29 ...U31, U33, U34, U41

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

Storage device name

Content

Notes

Quad SPI Flash

EEPROMSystem Controller CPLDDDR4 SDRAMeMMCProgrammable Clock Generator

Configuration Signals

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Overview of Boot Mode, Reset, Enables.

...

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
DDR4 SDRAM	not programmed
Quad SPI Flash	not programmed
EEPROM	not programmed besides factory programmed MAC address
Programmable Clock Generator	not programmed

Name

B2B/Connector

Direction

Description

Boot Mode

Enable

Reset

JTAGSEL

PGOOD

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown

B2B SoC/FPGA IOs

B2B JTAG Interface

B2B ETH Interface

B2B USB Interface

SD Card Connector

SMA Connector

MIO

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Note

title	Note

MIO section only for SoC devices with dedicated MIO, otherwhise remove this section

MIO Pins

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Only for SoC Modules(Xilinx MIO, for Intel and MicroChip SoC please change MIO to syntax of the manufacturer). you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

MIO Pins are only for SoC like Zynq, U+Zynq and Versal, for other FPGA modules remove this chapter

Example:

Table with all connectors and Designator
List of different interfaces per connector
IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Connector Type	Designator	Interface	IO CNT ¹⁾
B2B	JM1	MGT PL	4 x MGT (RX/TX)
B2B	JM1	HP	52 SE / 24 DIFF
B2B	JM2	MGT PS	2 x MGT CLK
B2B	JM2	MGT PS	4 x MGT (RX/TX)
B2B	JM2	CFG	JTAG
B2B	JM2	CFG	MODE
B2B	JM3	HD	48 SE / 24 DIFF
B2B	JM3	MGT PL	MGT CLK
B2B	JM3	MIO	65 GPIO
B2B	JM4	HP	104 SE / 48 DIFF

¹⁾ IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs

Test Points

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MIO PinConnected toB2BNotesMIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	B2B	Notes¹⁾
10TP1	PWR_PL_OKJ2-120

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connected to

Test Point	Signal		Notes¹⁾
TP1	PLL_SCL	pulled-up to PS_1V8
TP2	TP3	PLL_SDA	pulled-up to PS_1V8TP4
TP5	GND
TP6	PL_1V8
TP7	GND
TP8	GND
TP9	PL_VCCINT_IO
TP10

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueChip/InterfaceDesignatorNotes

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Power and Power-On Sequence

GND
TP11	PL_VCCINT
TP12	PL_VCU_0V9
TP13	FP_0V85
TP14	PS_1V8
TP15	GND
TP16	DDR_2V5
TP17	DDR_PLL
TP18	DDR_1V2
TP20	MGTAVTT
TP21	VTT
TP22	PL_GT_1V05
TP23	VREFA
TP24	MGTVCCAUX
TP25	MGTAVCC
TP27	PS_PLL
TP28	PS_AVTT
TP29	LP_0V85
TP30	PS_AUX
TP31	PS_AVCC
TP34	POR_B	pulled-up to PS_1V8

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

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Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_PWR_PCOBP
title-alignment	center
title	Power ConsumptionOn board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Input Pin

Typical Current

VIN

TBD*

* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title

anchor	Figure_PWR_PD
title-alignment	center
title	Power Distribution

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Chip/Interface	Designator	Connected To	Notes
DDR4 SDRAM	U2, U3, U9, U12	SoC - PS
Quad SPI Flash	U7, U17	SoC - PS	Booting.
EEPROM	U28	B2B - J2
Clock Generator	U5	SoC, B2B
Oscillator	U6	Clock Generator	25 MHz
Oscillator	U32	SoC	33.333333 MHz

Page properties

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

Anchor

	Configuration and System Control Signals
	Configuration and System Control Signals

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id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Power-On Sequence

Scroll Title

anchor	Figure_PWR_PS
title-alignment	center
title	Power Sequency

Scroll Ignore
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Scroll Only
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Voltage Monitor Circuit

Scroll Title

anchor	Figure_PWR_VMC
title-alignment	center
title	Voltage Monitor Circuit

Scroll Ignore
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Power Rails

B2B Connector

JM1

Scroll Title

anchor	Table_PWROV_PRCNTRL
title-alignment	center
title	Module power railsController signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name

Connector+Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

Bank Voltages

Scroll Title

anchor	Table_PWR_BV
title-alignment	center
title	Zynq SoC bank voltages.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

Bank

Schematic Name

Voltage

NotesBoard to Board Connectors Page properties

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id	Comments

This section is optional and only for modules.

Signal Name	Direction¹⁾	Description
JM1.A45	POR_OVERRIDE	IN	Override power-on reset delay ²⁾.
JM2.A31	ERR_OUT	OUT	PS error indication ²⁾.
JM2.A34	ERR_STATUS	OUT	PS error status ²⁾.
JM2.A35	LP_GOOD	OUT	Low-power domain powered-up. Pulled up to 3.3VIN
JM2.A36	PLL_SCL	IN	I2C clock
JM2.A37	PLL_SDA	IN/OUT	I2C data
JM2.A40	PG_VCU	OUT	Programmable logic powered-up.
JM2.A41	EN_PSGT	IN	Enable GTR transceiver power-up.
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47	TCK / TDI / TDO / TMS	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8
JM2.B29	PG_PSGT	OUT	GTR transceivers powered-up.
JM2.B30	PROG_B	IN/OUT	Power-on reset ²⁾. Pulled-up to PS_1V8.
JM2.B33	SRST_B	IN	System reset ²⁾. Pulled-up to PS_1V8.
JM2.B34	INIT_B	IN/OUT	Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.
JM2.B37	PG_PL	OUT	VCU powered-up.
JM2.B38	EN_FPD	IN	Enable full-power domain power-up.
JM2.B41	PG_FPD	OUT	Full-power domain powered-up.
JM2.B45	PG_DDR	OUT	DDR power supply powered-up.
JM2.B46	DONE	OUT	PS done signal ²⁾. Pulled-up to PS_1V8.
JM2.B47	EN_DDR	IN	Enable DDR power-up.
JM2.C31	MR	IN	Manual reset.
JM2.C35	EN_PL	IN	Enable programable logic power-up.
JM2.C36	EN_GT_R	IN	Enable GTH/GTY transceiver power-up.
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47	MODE3..0	IN	Boot mode selection ²⁾: JTAG QUAD-SPI (32 Bit) SD1 (2.0) eMMC (1.8 V) SD1 LS (3.0) Supported Modes depends also on used Carrier.
JM2.D33	PG_GT_R	OUT	GTH/GTY Transceivers powered-up.
JM2.D37	PSBATT	IN	PS RTC Battery supply voltage ^{2) 3)}.
JM2.D45 / JM2.D46	DX_P / DX_N	-	SoC temperatur sensing diode pins ²⁾.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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id	Comments

List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾
VCCO_66	JM1.A32 / JM1.A33	IN
VREF_66	JM1.A41	IN
3.3VIN	JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56	IN
PL_1V8	JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34	OUT
PL_DCIN	JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 /	IN
LP_DCDC	JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52	IN
DCDCIN	JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 /	IN
PS_BATT	JM2.D37	IN
DDR_1V2	JM2.D47	OUT
PS_1V8	JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56	OUT
GT_DCDC	JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 /	IN
VCCO_25	JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9	IN
VCCO_26	JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21	IN
VCCO_64	JM4.B21 / JM4.B39	IN
VREF_64	JM4.B30	IN
VCCO_65	JM4.C21 / JM4.C39	IN
VREF_65	JM4.C30	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH/GTY for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

Scroll Title

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title-alignment	center
title	Baseboard Design Hints

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Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
1 ²⁾	3.3VIN	3.3 V (± 5 %)	-	Management power supply.	Management module power supply. 0.5 A recommended. Consider note ²⁾ for modules with VCU and/or low-power SoC.
2	Processing System (PS):			Procedure for PS starting.
2.1	Low-power domain:			Bring-up for low-power domain PS.
2.1.1	LP_DCDC	3.3 V (± 5 %) ³⁾	-	Low-power domain power supply.	Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2	EN_LPD	-	PU ⁴⁾, 3.3 V	Low-power domain power enable.
2.1.3	LP_GOOD	-	PU ⁴⁾, 3.3 V	Low-power domain power good status.	Module power-on sequencing for low-power domain finished.
2.2	Full-power domain:			Bring-up for full-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.2.1	DCDCIN	3.3 V (± 5 %) ³⁾		Full-power domainand GTR transceiver power supply.	Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2	EN_FPD	3.3 V	-	Full-power domain power enable.
2.2.3	PG_FPD	-	PU ⁴⁾, 3.3 V	Full-power domain power good status.	Module power-on sequencing for full-power domain finished.
2.2.4	EN_DDR	3.3 V	-	DDR memory power enable.
2.2.5	PG_DDR		PU ⁴⁾, 3.3 V	DDR memory power good status.	Module power-on sequencing for DDR memory finished.
2.3	GTR Transceiver			Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1	EN_PSGT	3.3 V	-	GTR transceiver power enable.
2.3.2	PG_PSGT	-	PU ⁴⁾, 3.3 V	GTR transceiver power good status.	Module power-on sequencing for GTR transceiver finished.
2	Programmable Logic (PL)			Procedure for PL starting.	PS and PL can be started independently.
2.1	PL_DCIN	3.3 V (± 5 %) ³⁾ ⁵⁾	-	Programmable logic power supply.	Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2	EN_PL	-	PU ⁴⁾, 3.3 V	Programmable logic power enable.
2.3	PG_PL	-	PU ⁴⁾, 3.3 V	Programmable logic power good status.	Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4	VCCO_25 / VCCO_26 / VCCO_64 / VCCO_65 / VCCO_66	⁶⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.
2.5	PG_VCU	-	PU ⁴⁾, 3.3 V	VCU power good status.
3	GTH / GTY Transceiver			Procedure for GTH / GTY transceiver starting.	PL transceiver usage needs powered PL and low-power PS domain.
3.1	GT_DCDC	3.3 V (± 5 %) ³⁾	-	GTH / GTY transceiver power supply.	Main module power supply for GTH / GTY transceiver. 3 A recommended. Power consumption depends mainly on design and cooling solution.
3.2	EN_GT_R	3.3 V	-	GTH / GTY transceiver power enable.
3.3	PG_GT_R	-	PU ⁴⁾, 3.3 V	GTH / GTY transceiver power good status.

¹⁾ (optional)

²⁾ On TE0813 REV01 boards it is necessary for modules with VCU and/or low-power speedgrade to either connect signal EN_PL to voltage 3.3VIN or to enable EN_PL together with 3.3VIN. This should be changed in a newer revision.

³⁾ Dependent on the assembly option a higher input voltage may be possible.

⁴⁾ (on module)

⁵⁾ This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

⁶⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
PD:6 x 6 SoM LSHM B2B Connectors
PD:6 x 6 SoM LSHM B2B Connectors

Include Page

	PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors
	PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

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title	PS absolute maximum ratings

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
LP_DCDC	Micromodule Power	-0.300	6.0	V
DCDCIN	Micromodule Power	-0.300	7.0	V
GT_DCDC	Micromodule Power	-0.300	6.0	V
PL_DCIN ¹⁾	Micromodule Power	-0.300	4.0	V
3.3VIN	Micromodule Power	-0.300	3.600	V
PS_BATT	RTC / BBRAM	-0.500	2.000	V
VCCO_25	HD IO Bank power supply	-0.500	2.000	V
VCCO_26	HD IO Bank power supply	-0.500	2.000	V
VCCO_64	HP IO Bank power supply	-0.500	3.400	V
VCCO_65	HP IO Bank power supply	-0.500	3.400	V
VCCO_66	HP IO Bank power supply	-0.500	3.400	V
VREF_64	Bank input reference voltage	-0.500	2.000	V
VREF_65	Bank input reference voltage	-0.500	2.000	V
VREF_66	Bank input reference voltage	-0.500	2.000	V

¹⁾ This value depends highly on DCDC U4. Higher values are possible with different DCDCs. For more information consult schematic and according datasheets.

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be different depending on assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

use "include page" macro and link to the general B2B connector page of the module series,

For example: 6 x 6 SoM LSHM B2B Connectors
Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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anchor	Table_TS_AMRROC
title-alignment	center
title	PS absolute maximum ratingsRecommended operating conditions.

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Symbols

Parameter

Description

Min	Max

Unit

Units

V

Reference Document
LP_DCDC ¹⁾	3.135	3.465

VVV

V

VVV°C

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

See ???? datasheet

.


DCDCIN ¹⁾	3.135	3.465	V
GT_DCDC ¹⁾	3.135	3.465	V
PL_DCIN ¹⁾ ²⁾	3.135	3.465	V
3.3VIN	3.135	3.465	V
PS_BATT	1.2	1.5	V	See FPGA datasheet.
VCCO_25	1.164	3.399	V	See FPGA datasheet.
VCCO_26	1.164	3.399	V	See FPGA datasheet.
VCCO_64	0.97	1.854	V	See FPGA datasheet.
VCCO_65	0.97	1.854	V	See FPGA datasheet.
VCCO_66	0.97	1.854	V	See FPGA datasheet.
VREF_64	0.6	1.2	V	See FPGA datasheet.
VREF_65	0.6	1.2	V	See FPGA datasheet.
VREF_66	0.6	1.2	V	See FPGA datasheet.

¹⁾ Dependent on the assembly option a higher input voltage may be possible.

²⁾ This value depends highly on DCDC U4. Higher values may possible with different DCDCs. For more information consult schematic and according datasheets

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title	Recommended operating conditions.

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Parameter

Min

Max

Units

Reference Document

V

See ???? datasheets.

V

See ???? datasheet.

V

See ???? datasheet.

V

See ???? datasheet.

V

See ???? datasheet.

V

See ???? datasheet.

V

See ???? datasheet.

°C

Physical Dimensions

Module size: ?? 76 mm × ?? 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 5 mm.

PCB thickness: ?? mm1.74 mm (± 10 %).

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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title-alignment	center
title	Physical Dimension

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_TS_PD
simpleViewer	false
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tbstyle	top
lbox	true
diagramWidth	732
revision	2

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixedImage Added

Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706TE0813

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706TE0813

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title	Trenz Electronic Shop Overview

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cellHighlighting	true

Trenz shop TEXXXX TE0813 overview page
English page	German page

Revision History

Hardware Revision History

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Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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title	Board hardware revision number.
_HRN
title-alignment	center
title	Board hardware revision number.

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draw.io Diagram

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diagramName	Figure_RV_HRN
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lbox	true
diagramWidth	188
revision	2

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Image Added

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Date	Revision	Changes	Documentation Link
-	REV01	First Production Release	REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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Date

Revision

Contributor

Description

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infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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infoType	Current version
prefix	v.
type	Flat
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Page info

infoType	Modified by
type	Flat
showVersions	false

<add TRM change list here>Initial Document

--

all

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infoType	Modified users
type	Flat
showVersions	false

--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 3

New Version 4

Key

Overview

Key Features

Block Diagram

Block Diagram

Main Components

Main Components

Initial Delivery State

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

B2B SoC/FPGA IOs

B2B JTAG Interface

B2B ETH Interface

B2B USB Interface

SD Card Connector

SMA Connector

MIO

MIO Pins

Connectors

Test Points

Test Points

On-board Peripherals

On-board Peripherals

Power Supply

Power Consumption

Power Distribution Dependencies

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power-On Sequence

Voltage Monitor Circuit

Bank Voltages

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Technical Specifications

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)