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Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board" Date | Version | Changes | Author |
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2022-06-15 | 2.2 | - add 'QSPI-Boot mode'
- add 'Get prebuilt boot binaries'
- changed SD-Boot mode chapter
- 'Device Tree' chapter expanded
| TD | 2022-04-21 | 2.1 | | TD | 2022-02-28 | 2.0 | - add yocto to
- Overview → Key Features
- Overview → Requirements
- Design Flow
- Launch
- add section 'Software Design - Yocto'
| TD | 2021-06-15 | 1.2 | - table of content view
- template history
- placed a horizontal separation line under each chapter heading
- replaced <design name> by <project folder>
- changed title-alignment for tables from left to center
- update 19.x to 20.x
| JH,TD | 2020-11-24 | 1.1 | - add fix table of content
- add table size as macro
| JH | -- | 1.0 | -- | -- |
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Important General Note: Export PDF to download, if quartus revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
Key Features
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- Libero SoC v2022.2
- SoftConsole v2022.2-RISC-V-747
- PolarfireSoC MSS Configurator v2022.2
- HSS (Hardware System Service)
- Yocto
- UART
- ETH
- USB
- I2C
- QSPI flash
- DDR3 memory
- User LED
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Revision History
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- add design changes on description
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Date | Libero SoC | Project Built | Authors | Description |
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2023-04-30 | v2022.2 |
| Mohsen Chamanbaz | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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title | Known Issues |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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title | Software |
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Software | Version | Note |
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Libero SoC | v2022.2 | needed | SoftConsole | v2022.2 | needed | PolarfireSoC MSS Configurator | v2022.2 | needed | Yocto | Kirkstone | needed (more information: Yocto KICKstart#Used source files) |
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Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
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Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
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Module Model | Board Part Short Name | Yocto Machine Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TEM0007* | ?????? | tem0007 | REV01 | 1GB | 64MB | ---- | ---- | ---- |
*used as reference |
Design supports following carriers:
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title | Hardware Carrier |
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Carrier Model | Notes |
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TE0703TEM0703* | As carrier board. This board must be special for Microchip FPGAs. |
*used as reference |
Additional HW Requirements:
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title | Additional Hardware |
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Additional Hardware | Quantity | Notes |
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TE0790 XMOD | 1 | For HSS console | Mini USB cable for JTAG/UART | 2 | Check Carrier Board and Programmer for correct type | RJ45 Ethernet cable | 1 |
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*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - Intel devices
Design Sources
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Type | Location | Notes |
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Libero | <project folder>/source_files/Libero <project folder>/source_files/<Board Part Short Name>/Libero | Libero project will be generated by TE Scripts (Optional) Source files for specific assembly variants | SoftConsole | <project folder>/source_files/SoftConsole <project folder>/source_files/<Board Part Short Name>/SoftConsole | Additional software will be generated by TE Scripts (Optional) Source files for specific assembly variants | Yocto | <project folder>/source_files/os/yocto | Yocto BSP layer template for linux |
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Prebuilt
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- Template Table:
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File | File-Extension | Description |
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Libero Project File | *.prjx |
| FlashPro Express Job | *.job |
| Constraint File | *.pdc |
| Timing Constraint File | *.sdc |
| Components in Block Design | *.cxf |
| Configuration File | *.cfg |
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| Software-Application-File | *.elf | Software application for SoftConsole |
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| Device Tree | *.dtb | Device tree blob | CONF-File | *.conf | Boot configuration file (extlinux.conf) | Yocto linux image | *.wic | This File can be flashed via bmaptool on the SD card. | Yocto linux image | *.img | Linux image for SD card |
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Download
Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Libero Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
- Open create_project_win.cmd/create_project_linux.sh:
- Select Board in "Board selection"
- Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
- Create and configure your Yocto Linux project, see Yocto KICKstart
- Copy the generated meta-<module> folder from <project name>/os/yocto/meta-<module> to the path/to/yocto/poky/ directory
- Follow the steps from Yocto KICKstart#Create a project for an Intel FPGA device without running the 'bitbake' command
Add the generated bsp layer meta-<machine> to path/to/yocto/poky/build/conf/bblayers.conf with:
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bitbake-layers add-layer ../meta-<module> |
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Note: The generated meta-<module> layer depends on the meta-altera layer (for more information see: Yocto KICKstart#Used source files), so you need to add both bsp layers to bblayers.conf |
Redefine the variable MACHINE with '<module>-<Board-Part-Short-Name>' in path/to//yocto/poky/build/conf/local.conf. The correct MACHINE name can be found in the #Hardware table.
Also define the variables INITRAMFS_IMAGE_BUNDLE and INITRAMFS_IMAGE to generate a ram disk image.
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sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf
echo -e '\nMACHINE = "<module>-<Board-Part-Short-Name>"' >> conf/local.conf
echo -e '\nINITRAMFS_IMAGE_BUNDLE = "1"' >> conf/local.conf
echo -e 'INITRAMFS_IMAGE = "te-initramfs"' >> conf/local.conf |
Build the image with following command (the image recipes are located in meta-<module>/recipes-core/images/):
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bitbake te-image-minimal |
Launch
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Note: - Programming and Startup procedure
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Get prebuilt boot binaries
Note |
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Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
- Run create_project_win.cmd/create_project_linux.sh
- Select Module in 'Board selection'
- Click on 'Export prebuilt files' button
- Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened
SD-Boot mode
- Prepare SD card as follows for SD-Boot
Run following command to get the device name of the SD card (e.g. /dev/sdx):
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lsblk |
- Insert SD card in the SD card reader, unmount and erase it
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sudo umount /dev/sdx
sudo sfdisk --delete /dev/sdx |
Create required partitions on the SD card (partition 1: 50MB, FAT32 / partition 2: 2MB, a2)
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echo -e ',50M,c\n,2M,a2' | sudo sfdisk /dev/sdb --force
sudo mkfs.vfat -F 32 -n boot /dev/sdb1 |
Copy the u-boot file to partition 2 of the SD card
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sudo dd if=path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp of=/dev/sdb2 bs=1M seek=0
sync
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- Copy zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ via file manager to the partition 1 (named 'boot') on SD card
- Set Boot Mode to SD-Boot
- Depends on Carrier, see carrier TRM
- Insert SD-Card in the SD-Slot
QSPI-Boot mode
Option for u-boot-with-spl.sfp on QSPI flash and zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and extlinux/extlinux.conf on SD card.
Use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: #Get prebuilt boot binaries
- Connect JTAG and power on carrier with module
- Open path/to/intelFPGA_lite/21.1/embedded/Embedded_Command_Shell.bat ( Win OS)/path/to/intelFPGA_lite/21.1/embedded/embedded_command_shell.sh (Linux OS) from Intel SoC FPGA EDS
Run following commands:
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quartus_hps -c 1 -o pv -a 0x0 path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp |
- Copy zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ to SD card.
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM
- Insert the SD card in the SD-Slot
QSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd/create_project_linux.sh
- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
- Open Serial Console (e.g. PuTTY)
select COM Port
Info |
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Win OS: see device manager Linux OS: see dmesg | grep tty (UART is *USB1) |
- Speed: 115200
- Press reset button
- Console output depends on used Software project, see Software Design - SDK#Application
- Linux Console:
Login data:
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Note: Wait until Linux boot finished |
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Username: root
Password: root |
You can use Linux shell now.
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i2cdetect -y -r 1 (check I2C 1 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
- ...
System Design - Libero
Block Design
The block designs may differ depending on the assembly variant.
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Project |
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Platform Desginer |
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HPS Interfaces
Activated interfaces:
Type | Note |
DDR | -- |
EMAC0 | -- |
EMAC1 | -- |
GPIO0 | -- |
GPIO1 | -- |
GPIO2 | -- |
I2C0 | -- |
I2C1 | -- |
QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB0 | -- |
USB1 | -- |
CAN0 | -- |
CAN1 | -- |
Software Design - SoftConsole
Application
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---------------------------------------------------------- General Example: hello_tei0006Hello TEI0006 is a Hello World example as endless loop instead of one console output. |
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
...
Software Design - Yocto
For Yocto installation and project creation, follow instructions from:
U-Boot
Start with Create a custom BSP layer for Microchip SoC or FPGA#Configure u-boot
File location: meta-<module>/recipes-bsp/u-boot/
Changes:
Device Tree
U-boot Device Tree
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title | Excerpts from test_board/os/yocto/meta-<module_series>/recipes-bsp/u-boot/files/<module_series>_<Board_Part_Short_Name>/dts/<module_series>_<Board_Part_Short_Name>.dts |
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
/dts-v1/;
#include "microchip-mpfs.dtsi"
#include "dt-bindings/gpio/gpio.h"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
serial1 = &uart1;
ethernet0 = &mac0;
spi0 = &qspi;
};
chosen {
stdout-path = "serial1";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
ddrc_cache: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
};
&uart1 {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-debounce-delay-ms;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
};
&mac1 {
status = "disabled";
};
&mac0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@1 {
device-type = "ethernet-phy";
reg = <1>;
reset-names = "ETH_RST";
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
&qspi {
status = "okay";
num-cs = <1>;
flash0: spi-nor@0 {
compatible = "spi-nor";
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <20000000>;
spi-cpol;
spi-cpha;
};
};
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Kernel Device Tree
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
aliases {
ethernet0 = &mac0;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
//******************************************************//
ddrc_cache: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fabricbuf0ddrc: buffer@A0000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xA0000000 0x0 0x2000000>;
no-map;
};
};
udmabuf0 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-c0";
minor-number = <0>;
size = <0x0 0x2000000>;
memory-region = <&fabricbuf0ddrc>;
sync-mode = <3>;
};
//******************************************************//
usb_phy: usb_phy {
#phy-cells = <0>;
//compatible = "ulpi-phy";
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
reset-names = "OTG_RST";
};
soc {
};
};
&can0 {
status = "disabled";
};
&core_pwm0 {
status = "okay";
};
&fpgadma {
status = "okay";
};
&fpgalsram {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
eeprom: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
#address-cells = <1>;
#size-cells = <1>;
eth0_addr: eth-mac-addr@FA {
reg = <0xFA 0x06>;
};
};
};
&i2c2 {
status = "okay";
};
&mac0 {
status = "okay";
phy-mode = "sgmii";
nvmem-cells = <ð0_addr>;
nvmem-cell-names = "mac-address";
/delete-property/ local-mac-address;
phy-handle = <&phy0>;
phy0: ethernet-phy@1 {
device-type = "ethernet-phy";
reg = <1>;
reset-names = "ETH_RST";
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
&mac1 {
status = "disabled";
};
&mbox {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&qspi {
status = "okay";
num-cs = <1>;
};
&refclk {
clock-frequency = <125000000>;
};
&spi0 {
status = "okay";
};
&spi1 {
status = "disabled";
};
&usb {
status = "okay";
dr_mode = "otg";
phys = <&usb_phy PHY_TYPE_USB2>;
};
|
Kernel
Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernel
File location: meta-<module>/recipes-kernel/linux/
Changes:
Images
Image recipe for minimal console image
File location: meta-<module>/recipes-images/yocto/
Image recipes:
- te-image-minimal.bb: create minimal linux image
- te-initramfs.bb: required for building an image with initial RAM Filesystem
Added packages/recipes:
Rootfs
Used filesystem: Initial RAM Filesystem (initramfs)
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Scroll Title |
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anchor | Table_dch |
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title-alignment | center |
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title | Document change history |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Date | Document Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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|
| Page info |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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|
| Page info |
---|
infoType | Modified by |
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type | Flat |
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|
| - change listInitial release v2022.2
| -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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|
| -- |
|
Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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|