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Impact: Clock (U3) powers-up automatically when 3.3V is available. FPGA (U1) can only disable clock. FPGA-firmware-design needs to be checked by customer.
#4 Changed Load Switch TPS27081ADDCR (Q1) to Load Switch MP5077GG-Z (U17) and adapted circuit.
Type: Schematic Change
Reason: BOM Optimization.
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Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.
Impact: None.
#7 Changed power supervisor TPS3805H33DCKR (U11) to STM6710LWB6F and adapted
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circuits.
Type: Schematic Change
Reason: Improved power monitoring.
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