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The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.

 

 GT Clock LocationGT Clock(MHz)Clock SourceNotes
TE0712Quad_216 CLK0125CLK2Si5338 Clock is connected to GT CLK2 input
TE0715Quad_112 CLK1125CLK2Si5338 Clock is connected to GT CLK2 input
TE0741Quad_115 CLK0, Quad_116 CLK0125B2B JM3  Si5338

 

Step to Step to generate the IBERT core:

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