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The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx AMD Zynq-7000 SoC (XC7Z020).

Scroll Only (inline)
Refer to trenz.org/teb0729te0729-info for online version of this manual and additional technical documentation of the product.

Key Features

  • Industrial-grade Xilinx AMD Zynq-7000 (XC7Z020) SoM
    • Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
    • 136 x FPGA I/Os (58 LVDS pairs possible)
    • 8 x PS MIO pins
  • 16-bit wide 512 MByte DDR3 SDRAM
  • 32 MByte QSPI Flash memory
  • 4 GByte eMMC Flash memory
  • 1 x 10/100/1000 Mbps Ethernet transceiver PHY
  • 2 x 10/100 Mbps Ethernet transceiver PHYs
  • 3 x MAC address EEPROMs
  • Hi-speed USB 2.0 ULPI transceiver with full OTG support
  • Plug-on module with two 120-pin connectors
  • Evenly spread supply pins for good signal integrity
  • On-board high-efficiency DC-DC converters
    • 4.0 6 A x 1.0 V power rail
    • 1.5 3 A x 1.5 V power rail1.
    • 5 3 A x 1.8 V power rail
    • 1.5 3 A x 2.5 V power rail
  • System management
  • eFUSE bit-stream encryption
  • AES bitstream encryption
  • Temperature compensated RTC (real-time clock)
  • User LED
  • Rugged for shock and high vibration

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Block Diagram

Main Components

  1. Xilinx AMD Zynq-7000 all programmable SoC, U2
  2. 32 MByte quad SPI Flash memory, U13
  3. 4 Gbit DDR3/L SDRAM, U1
  4. Low-power RTC with battery backed SRAM, U22
  5. 1A 3 A PowerSoC DC-DC converter (1.5V), U26
  6. System Controller CPLD, U6
  7. Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U12
  8. Hi-speed USB 2.0 ULPI transceiver, U11
  9. Gigabit Ethernet (GbE) transceiver, U3
  10. Ultra-low supply-current voltage monitor, U21
  11. 2K I2C serial EEPROM with EUI-48™ node identity, U9
  12. 2K I2C serial EEPROM with EUI-48™ node identity, U20
  13. 2K I2C serial EEPROM with EUI-48™ node identity, U8
  14. 1A 3 A PowerSoC DC-DC converter (2.5V), U24
  15. 1A 3 A PowerSoC DC-DC converter (1.8V), U25
  16. 4A 6 A PowerSoC DC-DC converter (1.0V), U23
  17. 3A 3 A PFET load switch with configurable slew rate (3.3V), Q1 (position changed for REV03)
  18. Serial number (traceability) pad (position on bottom for REV03).
  19. Green LED D2 and red LED D8
  20. 10Base-T/100Base-TX Ethernet PHY, U19
  21. 10Base-T/100Base-TX Ethernet PHY, U17
  22. Low-power programmable oscillator @ 25.000000 MHz (ETH_CLKIN), U10
  23. 120-pin double-row REF-189019-02 B2B connector, J1J2
  24. Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U14
  25. SDIO port expander with voltage-level translation, U15
  26. eMMC NAND Flash, U5
  27. 120-pin double-row REF-189019-02 B2B connector, J2J1

Initial Delivery State

Storage device nameContentNotes

24AA025E48 EEPROMs

User content not programmed

Valid MAC address from manufacturer
eMMC Flash-MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed


SPI Flash main array

Demo design


eFUSE USER

Not programmed


eFUSE Security

Not programmed


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BankTypeB2BIO countIO VoltageNotes
500MIO

J2-87

J2-88

23,.3 VMIO0, MIO9
500MIO

J2-93

J2-95

J2-94

J2-96

43,.3 V

Configured as I2C1 and USART0 by default,

Configurable as GPIO by user

13HRJ148User
33HRJ148User
35HRJ2303,.3 V
34GPIOJ2102,.5 V

Configured as DISP_RX by default,

Configurable as GPIO by user

For detailed information about the pin out, please refer to the Master Pin-out table.

JTAG Interface

JTAG access to the Xilinx AMD Zynq-7000 device is provided through B2B connector J2.

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PHY PINZYNQ PSNotes
MDC/MDIOMIO52, MIO53-
LED0-pin J2-57 on B2B connector
LED1-pin J2-59 on B2B connector
LED2/InterruptMIO46-
CONFIG-Connected to GND, PHY Address 0
RESETnMIO51-
RGMIIMIO16..MIO27-
SGMII-B2B J2
MDI-B2B J2


The TE0729 SoM is also equipped is also equipped with two additional Microchip KSZ8081MLXCA Ethernet PHY's (IC's U17 and U19) to provide further 10/100 Mbps Ethernet interfaces with the identifiers Ethernet1 and Ethernet2. The reference clock input of both PHYs is supplied from the same 25MHz 25 MHz oscillator (U10), which also provides Ethernet0 Gigabit PHY with a reference clock signal.

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For startup, a power supply with minimum current capability of 3A 3 A is recommended.

VIN and 3.3VIN can be connected to the same source (3.3 V).

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BankVoltageMax. ValueNotes
5011,.8 V-ETH0 / USB0 / SDIO0
5003,.3 V-SPI / I2C / UART
5021,.5 V-DDR3-RAM
13user3,.3 Vconnected to 3,.3V by default by 0-Ohm-Resistor R36
33user3,.3 Vconnected to 3,.3V by default by 0-Ohm-Resistor R55
342,.5 V-ETH / DISP
353,.3 V-GPIO

Power-up sequence at start-up

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Pay attention to the voltage level of the I/O-signals, which must not be higher than VCCIO + 0.4V.

Warning
Power-up sequencing changed for REV03. Please, take a look at schematics (Power Overview) for REV03 power-up sequencing.

Board to Board Connectors

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Note
Assembly variants for higher storage temperature range on request


Note
Please check Xilinx AMD Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).

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ParameterMinMaxUnitsNotesReference document
VIN supply voltage23.51353.6465V

VBAT supply voltage1.85.5V

PL I/O bank supply voltage for HR I/O banks (VCCO)1.143.465V
Xilinx AMD document DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheetXilinx AMD document DS191 and DS187
Voltage on module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal

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  • Module size: 76 mm × 52 mm.

  • Mating height with standard connectors: 4,25 5 mm.

  • PCB thickness: 2 mm.

All dimensions are shown in millimeters.

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All parts are at least industrial temperature range of -40°C to +85°C.

 

The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Weight

Weight

Part

21,.6 g

Plain module

Revision History

Hardware Revision HistoryRevision History

Changes
DateRevisionChanges
2023-12-0103
  1. Changed DCDC (U24, U25, U26) from EN5311QI to MPM3834C.
  2. Changed DCDC (U23) from EN6347QI to MPM3860GQW-Z.
  3. Changed load switch (Q1) from TPS27082LDDCR to MP5077GG-Z.
  4. Added power supervisor (U4).
  5. Changed ferrid bead (L2... L7, L10... L13) from BKP0603HS121-T to MPZ0603S121HT000.
  6. Changed power net name from 1.5V to DDR_VDD.
  7. Changed power sequencing. 
    1. Voltage supervisor (U4) enables 1V voltage rail (DCDC U23) via signal EN_Module.
    2. 1V DCDC (U23) enables 1.8V voltage rail (DCDC U25) via signal PG_1V0.
    3. 1.8V DCDC (U25) enables 2.5V (DCDC U24) and DDR_VDD (DCDC U26) voltage rails via signal PG_1V8.
    4. Voltage rail 3.3V (load switch Q1) is logical AND-enabled via
      1. power good signal PG_2V5_3V3 from voltage rail 2.5V DCDC (U24) and DDR_VDD DCDC (U26) via diode (D4)
      2. CPLD (U6) signal EN_3V3 via diode (D5).
  8. Added level shifter in signal FPGA_IO (U7, C185, C186) to separate power domains. Added resistor R91 as fallback.
  9. Added diode D3 between U21 pin 3 net nRST_in and voltage rail 3.3V.
  10. Added option to improve noise immunity for signal nRST_in via capacitor C187 (default: not assembled).
  11. Connected exposed pad to GND for SDIO port expander (U15).
  12. Added decoupling capacitors:
    1. C166 for U2I.
    2. C178 for U2H.
    3. C167 and C173 for U11.
    4. C168... C171 for U3C.
    5. C172 and C179 for U5B.
    6. C174 for U15.
    7. C175 for U8.
    8. C176 for U9.
    9. C177 for U20.
  13. Changed 10 µF capacitors (C36, C86) to 22 µF.
  14. Changed 22 µF capacitors (C117, C121, C125, and C127) from size 0805 to 0603.
  15. Changed capacitor C144 from 470 nF, 6.3 V, X5R, 20 % to 100 nF, 16 V, X7R, 10 %.
  16. Pulled-up board revision signal (U2D pin H17) and added board revision documentation.
  17. Changed fiducials to standard fiducials.
  18. Removed serial number S/N.
  19. Added testpoints TP1...TP41.
  20. Added serial number box on bottom overlay.
  21. Changed signal trace length.
  22. Added revision history, block and power overview and additional information. Updated page count and order.
DateRevision
2016-05-0202First production release
 -

01

Prototypes

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

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Aug 2018
DateRevisionContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd


Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat


Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Changed Xilinx to AMD.
  • Updated to REV03.
  • Minor changes.

2022-07-13

v.30

Martin Rohrmüller

  • corrected VIN range table

2018-08-29

v.29John Hartfiel
  • update Links
2017-11-06v.28Ali Naseri
  • Updated B2B connector section.
2017-06-18
v.22
Jan Kumann
  • New product images.
2017-06-07
v.21
Jan Kumann
  • Minor re-formatting.

2017-05-22

v.12

Jan Kumann

  • Sections rearranged for common style.
  • New physical dimension images.
  • Hardware revision image added.
  • New block diagram.
2017-03-24v.11John Hartfiel
  • Correction: Boot Mode settings.
2016-06-14v.10

Ali Naseri

  • Initial release.

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