Page History
...
The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx AMD Zynq-7000 SoC (XC7Z020).
Scroll Only (inline) |
---|
Refer to trenz.org/teb0729te0729-info for online version of this manual and additional technical documentation of the product. |
Key Features
- Industrial-grade Xilinx AMD Zynq-7000 (XC7Z020) SoM
- Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
- 136 x FPGA I/Os (58 LVDS pairs possible)
- 8 x PS MIO pins
- 16-bit wide 512 MByte DDR3 SDRAM
- 32 MByte QSPI Flash memory
- 4 GByte eMMC Flash memory
- 1 x 10/100/1000 Mbps Ethernet transceiver PHY
- 2 x 10/100 Mbps Ethernet transceiver PHYs
- 3 x MAC address EEPROMs
- Hi-speed USB 2.0 ULPI transceiver with full OTG support
- Plug-on module with two 120-pin connectors
- Evenly spread supply pins for good signal integrity
- On-board high-efficiency DC-DC converters
- 4.0 6 A x 1.0 V power rail
- 1.5 3 A x 1.5 V power rail1.
- 5 3 A x 1.8 V power rail
- 1.5 3 A x 2.5 V power rail
- System management
- eFUSE bit-stream encryption
- AES bitstream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Rugged for shock and high vibration
...
Block Diagram
Main Components
- Xilinx AMD Zynq-7000 all programmable SoC, U2
- 32 MByte quad SPI Flash memory, U13
- 4 Gbit DDR3/L SDRAM, U1
- Low-power RTC with battery backed SRAM, U22
- 1A 3 A PowerSoC DC-DC converter (1.5V), U26
- System Controller CPLD, U6
- Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U12
- Hi-speed USB 2.0 ULPI transceiver, U11
- Gigabit Ethernet (GbE) transceiver, U3
- Ultra-low supply-current voltage monitor, U21
- 2K I2C serial EEPROM with EUI-48™ node identity, U9
- 2K I2C serial EEPROM with EUI-48™ node identity, U20
- 2K I2C serial EEPROM with EUI-48™ node identity, U8
- 1A 3 A PowerSoC DC-DC converter (2.5V), U24
- 1A 3 A PowerSoC DC-DC converter (1.8V), U25
- 4A 6 A PowerSoC DC-DC converter (1.0V), U23
- 3A 3 A PFET load switch with configurable slew rate (3.3V), Q1 (position changed for REV03)
- Serial number (traceability) pad (position on bottom for REV03).
- Green LED D2 and red LED D8
- 10Base-T/100Base-TX Ethernet PHY, U19
- 10Base-T/100Base-TX Ethernet PHY, U17
- Low-power programmable oscillator @ 25.000000 MHz (ETH_CLKIN), U10
- 120-pin double-row REF-189019-02 B2B connector, J1J2
- Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U14
- SDIO port expander with voltage-level translation, U15
- eMMC NAND Flash, U5
- 120-pin double-row REF-189019-02 B2B connector, J2J1
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROMs | User content not programmed | Valid MAC address from manufacturer |
eMMC Flash-Memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | Demo design | |
eFUSE USER | Not programmed | |
eFUSE Security | Not programmed |
...
Bank | Type | B2B | IO count | IO Voltage | Notes |
---|---|---|---|---|---|
500 | MIO | J2-87 J2-88 | 2 | 3,.3 V | MIO0, MIO9 |
500 | MIO | J2-93 J2-95 J2-94 J2-96 | 4 | 3,.3 V | Configured as I2C1 and USART0 by default, Configurable as GPIO by user |
13 | HR | J1 | 48 | User | |
33 | HR | J1 | 48 | User | |
35 | HR | J2 | 30 | 3,.3 V | |
34 | GPIO | J2 | 10 | 2,.5 V | Configured as DISP_RX by default, Configurable as GPIO by user |
For detailed information about the pin out, please refer to the Master Pin-out table.
JTAG Interface
JTAG access to the Xilinx AMD Zynq-7000 device is provided through B2B connector J2.
...
PHY PIN | ZYNQ PS | Notes |
---|---|---|
MDC/MDIO | MIO52, MIO53 | - |
LED0 | - | pin J2-57 on B2B connector |
LED1 | - | pin J2-59 on B2B connector |
LED2/Interrupt | MIO46 | - |
CONFIG | - | Connected to GND, PHY Address 0 |
RESETn | MIO51 | - |
RGMII | MIO16..MIO27 | - |
SGMII | - | B2B J2 |
MDI | - | B2B J2 |
The TE0729 SoM is also equipped is also equipped with two additional Microchip KSZ8081MLXCA Ethernet PHY's (IC's U17 and U19) to provide further 10/100 Mbps Ethernet interfaces with the identifiers Ethernet1 and Ethernet2. The reference clock input of both PHYs is supplied from the same 25MHz 25 MHz oscillator (U10), which also provides Ethernet0 Gigabit PHY with a reference clock signal.
...
For startup, a power supply with minimum current capability of 3A 3 A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
...
Bank | Voltage | Max. Value | Notes |
---|---|---|---|
501 | 1,.8 V | - | ETH0 / USB0 / SDIO0 |
500 | 3,.3 V | - | SPI / I2C / UART |
502 | 1,.5 V | - | DDR3-RAM |
13 | user | 3,.3 V | connected to 3,.3V by default by 0-Ohm-Resistor R36 |
33 | user | 3,.3 V | connected to 3,.3V by default by 0-Ohm-Resistor R55 |
34 | 2,.5 V | - | ETH / DISP |
35 | 3,.3 V | - | GPIO |
Power-up sequence at start-up
...
Pay attention to the voltage level of the I/O-signals, which must not be higher than VCCIO + 0.4V.
Warning |
---|
Power-up sequencing changed for REV03. Please, take a look at schematics (Power Overview) for REV03 power-up sequencing. |
Board to Board Connectors
...
Note |
---|
Assembly variants for higher storage temperature range on request |
Note |
---|
Please check Xilinx AMD Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex). |
...
Parameter | Min | Max | Units | Notes | Reference document |
---|---|---|---|---|---|
VIN supply voltage | 23.5135 | 3.6465 | V | ||
VBAT supply voltage | 1.8 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx AMD document DS191 | |
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx AMD document DS191 and DS187 |
Voltage on module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
...
Module size: 76 mm × 52 mm.
Mating height with standard connectors: 4,25 5 mm.
PCB thickness: 2 mm.
All dimensions are shown in millimeters.
...
All parts are at least industrial temperature range of -40°C to +85°C.
The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
Weight | Part |
---|---|
21,.6 g | Plain module |
Revision History
Hardware Revision HistoryRevision History
Date | Revision | Changes | |||
---|---|---|---|---|---|
2023-12-01 | 03 |
| Date | Revision | Changes|
2016-05-02 | 02 | First production release | |||
- | 01 | Prototypes |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
...
Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
| ||||||||||||||||||||||||||
2022-07-13 | v.30 | Martin Rohrmüller |
| ||||||||||||||||||||||||||
2018-08-29 | Aug 2018v.29 | John Hartfiel |
| ||||||||||||||||||||||||||
2017-11-06 | v.28 | Ali Naseri |
| ||||||||||||||||||||||||||
2017-06-18 | v.22 | Jan Kumann |
| ||||||||||||||||||||||||||
2017-06-07 | v.21 | Jan Kumann |
| ||||||||||||||||||||||||||
2017-05-22 | v.12 | Jan Kumann |
| ||||||||||||||||||||||||||
2017-03-24 | v.11 | John Hartfiel |
| ||||||||||||||||||||||||||
2016-06-14 | v.10 | Ali Naseri |
|
...