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FPGA PL Design can access the PS connected peripherals, they are visible on AXI bus from the FPGA.
| Note |
|---|
It is not possible to route PL Peripheral I/O to MIO pins. |
Overview
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FPGA PL Design can access the PS connected peripherals, they are visible on AXI bus from the FPGA.
| Note |
|---|
It is not possible to route PL Peripheral I/O to MIO pins. |