Page History

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Impact: None. Minor changes in electrical characteristics.

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#2 Changed DCDCs TPS82085SIL (U5, U6, U7, U8) to MPM3834CGPA-Z and adapted power circuit.

Type: Schematic Change

Reason: BOM Optimization.

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Impact: None. Increased current output capability. Minor changes in electrical characteristics.

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#4 Added power supervisor STM6710LWB6F (U12, U13) and connected System controller (U3) pin 25 to net "PG_SENSE" instead of 3.3 V.

Type: Schematic Change

Reason: Improve power monitoring.

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Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

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#6 Connect U14 to I2C bus via resistors (R91, R92) and pull-up resistors (R45, R47).

Type: Schematic Change

Reason: Improvement of DCDC handling.

Impact: None. I2C bus has additional device.

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#7 Added pull-up resistor (

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R72) for signal "

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PROG_

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B".

Type: Schematic Change

Reason: Add external pull-up resistor for write protect functionalitySetup PROGRAM_B_0 functionality externally.

Impact: None. Improve usable flash options.

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#8 Added pull-up resistor (R74) (default: fitted) and pull-down resistor (R75) (default: not fitted) for PUDC_B handling for signal "DATA4".

Type: BOM Schematic Change

Reason: EOL of componentFollow AMD recommendation.

Impact: None.

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#9 Added pull-up resistor (R71) for signal "SPI_DQ2".

Type: PCB changeSchematic Change

Reason: Result of changes aboveAdd external pull-up resistor for write protect functionality.

Impact:Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0713 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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None. Improve usable flash options.

#10 Added common mode voltage setting via resistors (R62, R64, R65,

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R66) for clock signals "PLL_CLK_P" and "PLL_CLK_N" termination.

Type: Schematic Change

Reason: Improve clock termination.

Impact: None.

#9 Added capacitor (C184) for FPGA.

Type: Schematic Change

Reason: Follow AMD recommendation.

Impact: None.

#9 Changed capacitor (C80, C177) from 47 µF, 6.3 V 0805 to 22 µF, 10 V, 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#9 Changed capacitor (C2, C4, C5, C53, C158) from 0805 to 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#9 Changed 100 µF capacitors (C35, C45, C120, C144, C145, C146, C147, C148, C149) from 6.3 V, X5R, 1206 to 4 V, X6S, 0805.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#9 Changed capacitor (C103, C104) from 50 V 0402 to 25 V, 0201.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

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#11 Connected signal "RD_N" to FPGA via level translator (U10).

Type: Schematic Change

Reason: Enable 245 Synchronous FIFO Mode.

Impact: None.

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#12 Added pull-up resistor (R63) for signal "

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OE_N".

Type: Schematic Change

Reason: Follow FTDI specificationDisable 245 Synchronous FIFO Mode.

Impact: None.

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#13 Added pull-up resistor (R76) option and pull-down resistor (R78)

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option for signal "GPIO_0".

Type: Schematic Change

Reason: Increase setting flexibility for FT600Q.

Impact: None.

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#14 Added pull-up resistor (R77) option and pull-down resistor (R79) option for signal "GPIO_1".

Type: Schematic Change

Reason: Increase setting flexibility for FT600Q.

Impact: None.

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#15 Added capacitor (C174) for signal "FTDI_RESET_N".

Type: Schematic Change

Reason: Follow AMD recommendationFTDI specification.

Impact: None.

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#16 Changed inductors from BKP0603HS121-T to MPZ0603S121HT000 for L1, L2, and L3.

Type: Schematic BOM Change

Reason:Disable 245 Synchronous FIFO ModeEOL of component.

Impact: None.

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#17 Added capacitor (C184) for FPGA.

Type: Schematic Change

Reason: Setup PROGRAM_B_0 functionality externallyFollow AMD recommendation.

Impact: None.

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#18 Added series termination resistor (R70) connecting signals "F_CK" and "FIFO_CLK".

Type: Schematic Change

Reason: Signal termination.

Impact: None.

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#19 Added series termination resistor (R73) connecting signals "SPI_SCK" and "SPI_SK".

Type: Schematic Change

Reason: Signal termination.

Impact: None.

#20 Changed capacitor (C80, C177) from 47 µF, 6.3 V 0805 to 22 µF, 10 V, 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#21 Changed capacitor (C2, C4, C5, C53, C158) from 0805 to 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#22 Changed 100 µF capacitors (C35, C45, C120, C144, C145, C146, C147, C148, C149) from 6.3 V, X5R, 1206 to 4 V, X6S, 0805.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#23 Changed capacitor (C103, C104) from 50 V 0402 to 25 V, 0201.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

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#24 Changed resistors (R2, R7, R8, R29, R67, R68) from 4.87 kOhm to 4.7 kOhm.

Type: Schematic Change

Reason: BOM optimization.

Impact: None.

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#25 Changed resistors (R53, R54) from 1 kOhm to 1.6 kOhm.

Type: Schematic Change

Reason: BOM optimization.

Impact: None.

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#26 Changed resistor (R3) from 0402 63 mW to 0201 50 mW.

Type: Schematic Change

Reason: BOM optimization.

Impact: None.

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#27 Removed testpoints from bottom PCB side for signals "3.3VIN", "RESIN", "JTAGEN", "TMS", "TCK", "TDI", and "TDO".

Type: Schematic Change

Reason: Optimize placement.

Impact: None.

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#28 Added testpoints (TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP30, TP31, TP32, TP33, TP34, TP39, TP40, TP(??? for AVCC).

Type: Schematic Change

Reason: Optimized placement.

Impact: None.

#29 Updated board revision decoding at FPGA pins L6 (BV1).

Type: Schematic Change

Reason: Update board revision identification.

Impact: None.

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#30 Updated components from library.

Type: Schematic Change

Reason: Use latest component data.

Impact: None.

#31 Signal trace lengths changed

Type: PCB change

Reason: Result of changes above.

Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0713 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

#32 Updated group tables and colours on "B2B-Connectors" page.

Type: Documentation Update

Reason: Documentation improvement.

Impact: None.

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#33 Added legal notices, system and power overview. Updated revision history. Updated page count and order. 

Type: Documentation Update

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