Page History

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Impact: None. Increased current output capability. Minor changes in electrical characteristics.

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#3 Changed HyperRAM (U4) from S27KS0641DPBHI000 to

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IS66WVH8M8ALL-166B1LI.

Type: BOM change

Reason: HyperRAM improvement.

Impact: None. ???

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None 

#4 Changed clock (U3) from SiT8008AI-73-XXS-100.000000E to SiT8008BI-73-XXS-100.000000E.

Type: Schematic Change

Reason: Use new clock revision.

Impact: None.

#5 Added jumper (J3) option (default: not fitted) and resistor (R36) to enable JTAG only boot mode.

Type: Schematic Change

Reason: QSPI programming problems with newer Vivado versions.

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Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

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#7 Added diode (D4) between voltage monitor (U9) pin 3 net "nRST" and voltage rail 3.3V.

Type: Schematic Change

Reason: Protect manual reset pin.

Impact: None.

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#8 Added pull-up resistor (R37) for signal "H1_A3".

Type: Schematic Change

Reason: Setup CS# signal externally.

Impact: None.

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#9 Set resistor (R13) to not fitted.

Type: BOM Change

Reason: BOM Optimization.

Impact: None.

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#10 Changed inductor (L1, L2, L3, L4, L6) from BKP0603HS121-T to MPZ0603S121HT000.

Type: BOM Change

Reason:EOL of component.

Impact: None.

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#11 Added testpoint (TP1, ..., TP10).

Type: Schematic Change

Reason: Voltage and system monitoring improvement.

Impact: None.

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#12 Removed track-it traceability pad S/N.

Type: Schematic Change

Reason: EOL of Component.

Impact: None.

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#13 Changed fiducials to standard fiducial type.

Type: Schematic Change

Reason: Use standard fiducials.

Impact: None.

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#14 Updated components from library.

Type: Schematic Change

Reason: Use latest component data.

Impact: None.

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#15 Added legal notices, system and power overview. Updated revision history. Updated page count and order. 

Type: Documentation Update

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