Versions Compared
Key
- This line was added.
- This line was removed.
- Formatting was changed.
Custom_table_size_100 |
---|
Page properties | ||||
---|---|---|---|---|
| ||||
Template Revision 2.1 Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
|
Overview
CPLD Device with designator U5: LCMX02-1200HC.
Feature Summary
- JTAG
- UART
- I2C
- Power
- Boot Mode
- Reset
- SD
- LED
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
---|---|---|---|---|---|
UART_TXD | in | 77 | NONE | 3.3V | UART0 TX / Sends data to MIO13. MIO13 is connected to B2B JB1 Pin 98. ( HSS console ) |
UART_RXD | out | 84 | NONE | 3.3V | UART0 RX / Recieves data from MIO12. MIO12 is connected to B2B JB1 Pin 100. ( HSS console ) |
CM0 | in | 76 | UP | 3.3V | DIP switch S2-2 / used as JTAG Selection/ If CM0 set to high (S2-2 OFF) → Access to CPLD of module otherwise access to FPGA of module. |
CM1 | in | 75 | UP | 3.3V | DIP switch S2-1 / Used to change PGOOD pin state /If CM1 set to high (S2-1 OFF) → PGOOD = '1' otherwise '0' |
EN1 | out | 81 | NONE | 3.3V | B2B Power Enable |
FL_0 | inout | 28 | NONE | 3.3V | LED (D3-red) / Status |
FL_1 | inout | 27 | NONE | 3.3V | LED (D4-green) / Status |
FT_B_RX | out | 138 | NONE | 3.3V | FTDI UART RX (UART1 RX) |
FT_B_TX / BDBUS0 | in | 139 | UP | 3.3V | FTDI UART TX (UART1 TX) |
JTAGEN | --- | 120 | --- | 3.3V | Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3 |
M_TCK | in | 131 | NONE | 3.3V | JTAG from/to FTDI |
M_TDI | in | 136 | NONE | 3.3V | JTAG from/to FTDI |
M_TDO | out | 137 | NONE | 3.3V | JTAG from/to FTDI |
M_TMS | in | 130 | NONE | 3.3V | JTAG from/to FTDI |
MIO0 | in | 94 | UP | 3.3V | DIP-S4 and B2B JB1 Pin 88. This signal is connected to MODE signal. |
MIO12 | in | 100 | NONE | 3.3V | Sends data to UART_RX |
MIO13 | out | 99 | NONE | 3.3V | Read data from UART_TX |
MIO14 | out | 105 | NONE | 3.3V | Receives data from FT_B_TX of FTDI chip |
MIO15 | in | 95 | NONE | 3.3V | Sends data to FT_B_RX of FTDI chip |
MIO9 | out | 96 | NONE | 3.3V | SD_CD signal is directed to this signal in firmware. |
MODE | out | 83 | NONE | 3.3V | Dip switch S2-4 is connected to MODE pin ( B2B-JB1-31) |
NOSEQ | inout | 78 | UP | 3.3V | NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux. |
PGOOD | inout | 82 | UP | 3.3V | PGOOD can be set or reset via CM1 ( dip switch S2-1) |
PHY_LED1 | out | 86 | DOWN | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED1R | out | 92 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED2 | out | 85 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED2R | out | 91 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PROGMODE | out | 104 | UP | 3.3V | Enable B2B Module JTAG access to CPLD for Firmware update |
RESIN | out | 119 | NONE | 3.3V | Module Reset Pin on B2B connector |
S1 | in | 114 | UP | 3.3V | Push Button / Used as module Reset |
SD_CD | in | 93 | UP | 3.3V | Forwarded to MIO9 |
SD_SEL | out | 113 | NONE | 3.3V | Set to GND / currently_not_used |
TCK_B | out | 1 | NONE | 3.3V | JTAG from/to Module |
TDI_B | out | 3 | NONE | 3.3V | JTAG from/to Module |
TDO_B / C_TDO | in | 2 | UP | 3.3V | JTAG from/to Module |
TMS_B | out | 4 | NONE | 3.3V | JTAG from/to Module |
ULED1 | out | 117 | NONE | 3.3V | LED (D1-red) / Shows the status of PGOOD, CM0 or shows the UART1 RX. |
ULED2 | out | 115 | NONE | 3.3V | LED (D2-green) / Shows the status of PGOOD, CM0 or shows the UART1 TX. |
X16 | in | 59 | UP | 3.3V | currently_not_used |
X17 | out | 60 | NONE | 3.3V | currently_not_used |
SDA / MIO11 | inout | 97 | UP | 3.3V | I2C Data |
SCL /MIO10 | in | 98 | UP | 3.3V | I2C Clock (100kHz) |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module). TEB2000 CPLD can be selected with JTAGEN (DIP-S2-3). Module FPGA/CPLD access can be switched with PROGMODE which is driven by CM0 (DIP-S2-2).CM0 is pulled up with CPLD.
S2-2 | S2-3 | PROGMODE (S2-2) | JTAGEN (S2-3) | Description |
---|---|---|---|---|
OFF | OFF | 1 | 1 | Access to TE0703 CPLD |
OFF | ON | 1 | 0 | Access to CPLD of B2B Module |
ON | OFF | 0 | 1 | Access to TE0703 CPLD |
ON | ON | 0 | 0 | Access to FPGA of B2B Module |
Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.
DIP Switch
DIP Switch S2 | ||||
---|---|---|---|---|
S2-1 | S2-2 | S2-3 | S2-4 | Description |
CM1 | CM0 | JTAGEN | MIO0 | JTAGEN set carrier board CPLD into the chain for firmware update. |
EN1
EN1 is set to one.
NOSEQ
NOSEQ pulled up to 3.3V. NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux.
NOSEQ | Connected to | Related command in linux console | Description |
---|---|---|---|
'0' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x00 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x00 |
'1' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x01 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x01 |
To read NOSEQ, GPIO_input[16] must be read. To read this bit the following instruction must be executed in linux console:
i2cget -y <related bus> 0x20 0x02
For example --> i2cget -y 0 0x20 0x02
PGOOD
PGOOD pulled up to 3.3V. PGOOD pin can be set or reset by user. If CM1 set to high (S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.
PGOOD | Condition | Description |
---|---|---|
'0' | CM1 = '0' | Dip switch S2-1 ON |
'1' | CM1 = '1' | Dip switch S2-1 OFF |
Reset
RESIN is driven by S1 (Push Button). Button is debounced.
Boot Mode
MODE pin is sourced by MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP. PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:
S2-1 | S2-4 | PGOOD | MIO0 | Description |
---|---|---|---|---|
ON | ON | 0 | 0 | JTAG boot mode |
OFF | ON | 1 | 0 | SD Card boot mode, PHY LEDs glow orange |
OFF | OFF | 1 | 1 | QSPI boot mode, PHY LEDs glow green |
UART
Primary UART:
MIO14 is driven by BDBUS0 (FTDI RX).
BDBUS1 (FTDI TX) is driven by MIO15 .
Secondary UART:
MIO13 is driven by X16.
X17 is driven by MIO12.
SD
SD selection is set to GND (SD Card slot).
MIO9 is switched to SD_CD and its status depends on SD_CD .
LED
LED Priority is order of the description
LED | Prio 0: Power | Prio 1: Modul CPLD access* | Prio 2 |
---|---|---|---|
LED1 (D1-red) | Blink, if Power Good is low | ON | FTDI UART RX |
LED2 (D2-green) | Blink, if Power Good is low | ON | FTDI UART TX |
LED3 (D3-red) | OFF | ON | User defined with B2B Pin JB2-99 |
LED4 (D4-green) | OFF | ON | User defined with B2B Pin JB2-90 |
PHY LEDs (green/orange) | Blink orange, if Power Good is low | Blink Green and orange | Green: Boot Mode set to QSPI, Orange: Boot Mode set to SD |
*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!
Appx. A: Change History and Legal Notices
Revision Changes
REV02 to REV03Oscillator frequency is changed from 12.09 MHz to 24.18 MHZ.
Access to CPLD of TE0715 with a generic parameter added. (For optional jed file to access CPLD of TE0715 module)
PGOOD used as second boot mode selector pin and connected to dip switch S2-1. PGOOD and MODE are boot mode selector pins.
- CM1 (Dip switch S2-2) has no effect on MIO9 anymore. That means MIO9 is connected to SD_CD only and not to SD_CD and CM1. REV02 to older REV01
- Enable CPLD access to module CPLD over DIP
- Add MIO0, SD_SEL, SD_CD, NOSEQ, PGOOD, 2LEDs, PHY LEDs
- Debounce button
- More status LED functionality
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties | ||||
---|---|---|---|---|
| ||||
|
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV03REV01 | REV05, REV06REV01 |
| REV03
| SC-PGM-TE0703-0506_CARRIER-03_20220815.zip)||||||||||||||||||||||
2019-11-08 | v.13 | REV02 | REV02*,REV03*,REV04*,REV05, REV06 *some IOs are not connected *SD_CD not available, set S2-1 to on | John Hartfiel |
| 2017-10-13 | REV02 | REV02*,REV03*,REV04*,REV05 |
| ||||||||||||||||||
2016-04-11 | v.1 | REV02 | REV02*,REV03*,REV04*,REV05 |
| |||||||||||||||||||||||
All | John Hartfiel
|
Appx. B: Legal Notices
Include Page | ||||
---|---|---|---|---|
|
Scroll Only | ||
---|---|---|
|
Scroll pdf ignore | ||||||
---|---|---|---|---|---|---|
|