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Template Revision 2.1 Design Name always "TE Series Name" + optional CPLD Name + "CPLD" - Change List 2.0 to 2.1
- Fix problem with pdf export and side scroll bar
- Change List 1.9.1 to 2.0
- add fix table of content
- add table size as macro
- removed page initial creator
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Overview
CPLD Device with designator U5: LCMX02-1200HC.
Feature Summary
- JTAG
- UART
- I2C
- Power
- Boot Mode
- Reset
- SD
- LED
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
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UART_TXD | in | 77 | NONE | 3.3V | UART0 TX / Sends data to MIO13. MIO13 is connected to B2B JB1 Pin 98. ( HSS console ) |
UART_RXD | out | 84 | NONE | 3.3V | UART0 RX / Recieves data from MIO12. MIO12 is connected to B2B JB1 Pin 100. ( HSS console ) |
CM0 | in | 76 | UP | 3.3V | DIP switch S2-2 / used as JTAG Selection/ If CM0 set to high (S2-2 OFF) → Access to CPLD of module otherwise access to FPGA of module. |
CM1 | in | 75 | UP | 3.3V | DIP switch S2-1 / Used to change PGOOD pin state /If CM1 set to high (S2-1 OFF) → PGOOD = '1' otherwise '0' |
EN1 | out | 81 | NONE | 3.3V | B2B Power Enable |
FL_0 | inout | 28 | NONE | 3.3V | LED (D3-red) / Status |
FL_1 | inout | 27 | NONE | 3.3V | LED (D4-green) / Status |
FT_B_RX | out | 138 | NONE | 3.3V | FTDI UART RX (UART1 RX) |
FT_B_TX / BDBUS0 | in | 139 | UP | 3.3V | FTDI UART TX (UART1 TX) |
JTAGEN | --- | 120 | --- | 3.3V | Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3 |
M_TCK | in | 131 | NONE | 3.3V | JTAG from/to FTDI |
M_TDI | in | 136 | NONE | 3.3V | JTAG from/to FTDI |
M_TDO | out | 137 | NONE | 3.3V | JTAG from/to FTDI |
M_TMS | in | 130 | NONE | 3.3V | JTAG from/to FTDI |
MIO0 | in | 94 | UP | 3.3V | DIP-S4 and B2B JB1 Pin 88. This signal is connected to MODE signal. |
MIO12 | in | 100 | NONE | 3.3V | Sends data to UART_RX |
MIO13 | out | 99 | NONE | 3.3V | Read data from UART_TX |
MIO14 | out | 105 | NONE | 3.3V | Receives data from FT_B_TX of FTDI chip |
MIO15 | in | 95 | NONE | 3.3V | Sends data to FT_B_RX of FTDI chip |
MIO9 | out | 96 | NONE | 3.3V | SD_CD signal is directed to this signal in firmware. |
MODE | out | 83 | NONE | 3.3V | Dip switch S2-4 is connected to MODE pin ( B2B-JB1-31) |
NOSEQ | inout | 78 | UP | 3.3V | NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux. |
PGOOD | inout | 82 | UP | 3.3V | PGOOD can be set or reset via CM1 ( dip switch S2-1)
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PHY_LED1 | out | 86 | DOWN | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals.
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PHY_LED1R | out | 92 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals.
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PHY_LED2 | out | 85 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals.
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PHY_LED2R | out | 91 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals.
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PROGMODE | out | 104 | UP | 3.3V | Enable B2B Module JTAG access to CPLD for Firmware update |
RESIN | out | 119 | NONE | 3.3V | Module Reset Pin on B2B connector |
S1 | in | 114 | UP | 3.3V | Push Button / Used as module Reset |
SD_CD | in | 93 | UP | 3.3V | Forwarded to MIO9 |
SD_SEL | out | 113 | NONE | 3.3V | Set to GND / currently_not_used |
TCK_B | out | 1 | NONE | 3.3V | JTAG from/to Module |
TDI_B | out | 3 | NONE | 3.3V | JTAG from/to Module |
TDO_B / C_TDO | in | 2 | UP | 3.3V | JTAG from/to Module |
TMS_B | out | 4 | NONE | 3.3V | JTAG from/to Module |
ULED1 | out | 117 | NONE | 3.3V | LED (D1-red) / Shows the status of PGOOD, CM0 or shows the UART1 RX. |
ULED2 | out | 115 | NONE | 3.3V | LED (D2-green) / Shows the status of PGOOD, CM0 or shows the UART1 TX. |
X16 | in | 59 | UP | 3.3V | currently_not_used |
X17 | out | 60 | NONE | 3.3V | currently_not_used |
SDA / MIO11 | inout | 97 | UP | 3.3V | I2C Data |
SCL /MIO10 | in | 98 | UP | 3.3V | I2C Clock (100kHz) |
Functional Description
Dip Switch
DIP Switch S2 |
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S2-1 | S2-2 | S2-3 | S2-4 | Description |
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CM1 | CM0 | JTAGEN | MIO0 | JTAGEN set carrier board CPLD into the chain for firmware update. |
JTAG
JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module). TEB2000 CPLD can be selected with JTAGEN (DIP-S2-3). Module FPGA/CPLD access can be switched with PROGMODE which is driven by CM0 (DIP-S2-2). CM1 and CM0 are pulled up in CPLD.
S2-2 | S2-3 | CM0 (PROGMODE) (S2-2) | JTAGEN (S2-3) | Description |
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OFF | OFF | 1 | 1 | Access to TEB2000 CPLD |
OFF | ON | 1 | 0 | Access to CPLD of B2B Module |
ON | OFF | 0 | 1 | Access to TEB2000 CPLD |
ON | ON | 0 | 0 | Access to FPGA of B2B Module |
Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.
EN1
EN1 is set to one.
NOSEQ
NOSEQ pulled up to 3.3V. NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux.
NOSEQ | Connected to | Related command in linux console | Description |
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'0' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x00 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x00 |
'1' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x01 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x01 |
To read the NOSEQ status, GPIO_input[16] must be read like the following instruction:
i2cget -y <related bus> 0x20 0x02
For example --> i2cget -y 0 0x20 0x02
PGOOD
PGOOD pulled up to 3.3V. PGOOD pin can be set or reset by user. If CM1 set to high (S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.
PGOOD | Condition | Description |
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'0' | CM1 = '0' | Dip switch S2-1 ON |
'1' | CM1 = '1' | Dip switch S2-1 OFF |
Reset
RESIN is driven by S1 (Push Button). Button is debounced.
Pin | CPLD Pin | Connected to | Description |
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RESIN | 119 | B2B JB2 Pin 17 | Active-low |
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Boot Mode
MODE pin is sourced by MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP. PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:
S2-1 | S2-4 | PGOOD | MIO0 | Description |
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ON | ON | 0 | 0 | JTAG boot mode |
OFF | ON | 1 | 0 | SD Card boot mode, PHY LEDs glow orange |
OFF | OFF | 1 | 1 | QSPI boot mode, PHY LEDs glow green |
UART
MIO14 is driven by BDBUS0 (FTDI RX). BDBUS1 (FTDI TX) is driven by MIO15 . MIO13 is driven by UART_TXD. UART_RXD is driven by MIO12.
UART 0 (HSS Console) |
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CPLD UART Input Pin | CPLD Pin | Connected to | CPLD UART Output Pin | CPLD Pin | Connected to | Description |
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MIO12 | 100 | B2B-JB1-100 | UART_RXD | 84 | U8-Pin 11 |
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UART_TXD | 77 | U8-Pin 13 | MIO13 | 99 | B2B-JB1-98 |
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UART 1 (Linux Console) |
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CPLD UART Input Pin | CPLD Pin | Connected to | CPLD UART Output Pin | CPLD Pin | Connected to | Description |
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FT_B_TX | 139 | FTDI Chip U4 Pin 32 | MIO14 | 105 | B2B-JB1-91 |
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MIO15 | 95 | B2B-JB1-86 | FT_B_RX | 138 | FTDI Chip U4 Pin 33 |
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SD
SD selection is set to GND (SD Card slot). MIO9 is switched to SD_CD and its status depends on SD_CD .
On-board
LEDLEDs
RJ45 Connector LED | Designator | LED Status | Condition | Description |
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PHY_LED1 (Green LED Anode, Yellow LED Cathode)
PHY_LED1R (Green LED Cathode, Yellow LED Anode) | J14B
| Blinky Fast blink yellow | PGOOD = '0' |
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Slow blink yellow green | CM0='1' → Access to CPLD of Module |
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Green | MIO0 = '1' |
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yellow | MIO0 = '0' |
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PHY_LED2 (Green LED Cathode, Yellow LED Anode) PHY_LED2R (Green LED Anode, Yellow LED Cathode)
| J14C | Fast blink yellow | PGOOD = '0' |
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Slow blink yellow green | CM0='1' → Access to CPLD of Module |
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Green | MIO0 = '1' |
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yellow | MIO0 = '0' |
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LED | Designator | LED Status | Condition | Description |
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ULED1 (Red) | D1 | Blink, if Power Good is low |
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ON |
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FTDI UART RX |
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ULED2 | ULED2 (Green) | D2 | Blink, if Power Good is low |
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ON |
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FTDI UART TX |
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FL_0 (Red) | D3 | OFF |
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ON |
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User defined with B2B Pin JB2-99 |
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FL_1 (Green) | D4 |
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LED Priority is order of the description
LED | Prio 0: Power | Prio 1: Modul CPLD access* | Prio 2 |
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LED1 (D1-red) | Blink, if Power Good is low | ON | FTDI UART RX |
LED2 (D2-green) | Blink, if Power Good is low | ON | FTDI UART TX |
LED3 (D3-red) | OFF | ON | User defined with B2B Pin JB2-99 |
LED4 (D4-green) | OFF | ON | User defined with B2B Pin JB2-90 |
PHY LEDs (green/orange) | Blink orange, if Power Good is low | Blink Green and orange | Green: Boot Mode set to QSPI, Orange: Boot Mode set to SD |
*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!OFF |
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ON |
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User defined with B2B Pin JB2-90 |
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I2C to GPIO
I2C to GPIO is a subsystem in firmware of CPLD that provides an i2c interface that writes received data to GPIO_output 8 bit registers or reads 8 bit GPIO_input registers and send read data to i2c bus.
Scroll Title |
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title-alignment | center |
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title | I2C to GPIO |
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draw.io Diagram |
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border | true |
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diagramName | TEB2000_I2C_to_GPIO_Blockdiagramm |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 1071 |
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revision | 2 |
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I2C bus is connected to MIO10 ( SCL signal) and MIO11 (SDA signal). MIO10 to MIO15 are direct connection between CPLD of TEB2000 and FPGA on the module (for example TEM0007) through B2B connector. If in FPGA design exists no i2c interface for MIO10 and MIO11, this block will be unused. More information about MIO10 to MIO15 are shown in the following table for TEM0007 modules and TEB2000 carrier board:
B2B Pin | B2B JB1-96 | B2B JB1-94 | B2B JB1-100 | B2B JB1-98 | B2B JB1-91 | B2B JB1-86 |
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Carrier board | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Description |
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TEB2000 | MIO10 / I2C-SCL | MIO11 / I2C-SDA | MIO12 / GPIO | MIO13 / GPIO | MIO14 / UART0-RX | MIO15 / USRT0-TX | MIO10 and MIO11 are used in CPLD firmware as I2C SCL and SDA respectively. |
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B2B Pin | B2B JM1-95 | B2B JM1-93 | B2B JM1-99 | B2B JM1-97 | B2B JM1-92 | B2B JM1-85 |
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Module | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Description |
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TEM0007 | I2C_CON_SCL / A3 | I2C_CON_SDA / E3 | UART_CON_TX / C2 | USRT_CON_RX / D3 | UART_RX / H2 | UART_TX / H5 | MIO10 and MIO11 are already set in test_design of |
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There are more additional connections between CPLD and FPGA on the module , that are listed in the following table:
CPLD Pin | Carrier board B2B Pin | Module B2B Pin | In firmware used as | Description
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X6 | B2B JB1-84 | B2B JM1-83 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(31) ) |
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Y0 | B2B JB2-76 | B2B JM2-75 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(24) ) |
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Y1 | B2B JB2-78 | B2B JM2-77 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(25) ) |
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Y2 | B2B JB2-82 | B2B JM2-81 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(26) ) |
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Y3 | B2B JB2-84 | B2B JM2-83 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(27) ) |
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Y4 | B2B JB2-86 | B2B JM2-85 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(28) ) |
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Y5 | B2B JB2-88 | B2B JM2-87 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(29) ) |
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Y6 | B2B JB2-90 | B2B JM2-89 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(30) ) |
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I2C to GPIO registers access methods
I2C to GPIO registers
Appx. A: Change History and Legal Notices
Revision Changes
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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| REV01 | REV01
| Page info |
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| modified-user |
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| modified-user |
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| - REV01 release
- Firmware release (*.zip)
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Appx. B: Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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