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Template Revision 1.1

For carrier - module combination, create main getting started page for carrier Design Name always "TE Series Name" +Getting Started, for example "TE0701 Getting started" and add carrier/module combination in the description → link on the module resource page also

For whole board,  use the board name, for example "TEBF0911 Getting Started"

  • Change List 1.0 to 1.1
    • add table of content to sidebar


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In this section you must explain how to power on the board and run the Reference Design (test board) on the particular module. The main points must be mentioned are:

  • Overview of the board (point out the LEDs, Ethernets, Switches and etc on the board overview)
  • Explain Switches functionality
  • Explain user LEDs

  • Explain the UART connection

  • Refer to the Reference Design

    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


TEB2000 with TEM0007

Overview

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Board Overview

NumberNote
1J14- Ethernet interface
2J5,J8,J9,J10- Bank voltage adjustment
3JB1,JB2,JB3- B2B connector
4J3- SD card socket
5J21- UART0 socket
6J4- UART1 socket
7J13- 5V voltage input
8J12- USB stick socket
9S6- Reset button (SRST) (Soft reset)
10S1- Reset button ( Hard reset)
11S2- Dip Switch
12U4- CPLD Chip

Power supply

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The input power supply must be mentioned.

Single 5V power supply with minimum current capability of 1.5A is recommended to power on the board. 

DIP-Switches and Push Buttons

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Explain all DIP switches functionality.

There is two switch (S1 and S6) which is connected to RESET signals, these reset the system entirely. The S6 is a soft reset buttom and S1 create a reset signal via hardware.

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SignalDesignatorConnected toActive LevelDescription
SRSTS6B2B JB2 pin 56Active low
S1S1CPLD chip pin 114Active low
Dip Switch S2SignalPosition ONPosition OFFConnected toDescription
S2-1MIO0MODE pin ( B2B JB1 pin 31 set to '0')MODE pin ( B2B JB1 pin 31 set to '1')CPLD Chip pin 94 / B2B JB1 pin 88 
S2-2JTAGENModule FPGA  JTAG access ( if S2-3 ON)Module CPLD JTAG access (if S2-3 ON)CPLD chip pin 120
S2-3CM0Module FPGA/CPLD  JTAG access (depends on S2-3)Carrier CPLD  JTAG accessCPLD chip pin 76
S2-4CM1PGOOD signal set to '0'PGOOD signal set to '1'CPLD chip pin 75

There is no DIPs on TEM0007 module.

Jumpers

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Explain all Jumpers functionality and connection.


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DesignatorConnected toDefault set toNote
J5VCCIOAM1.8VOUTIt can be set to both 1.8V or 3.3V for TEM0007 module.
J8VCCIOBM1.8VOUTMay be set to either 3.3V or 1.8V. If set to 1.8V --> VDDAUX1 (TP5) = 2.5V±3%
J9VCCIOCM1.8VOUTIt can be set to both 1.8V or 3.3V for TEM0007 module.
J10VCCIODM1.8VOUTImportant note: Only set to 1.8V for TEM0007 module.


LEDs

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Explain all user LEDs functionality and connections.

There are three user LEDs which can be used for variant purposes.

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DesignatorColorConnected toB2BActive LevelNote




















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DesignatorColorConnected toActive LevelNote












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DesignatorColorConnected toActive LevelNote











JTAG/UART

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Explain JTAG or UART connection breifly.

JTAG and UART connections are available through mini USB connector.

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titleUART

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Designator

Connected to

B2B Pin

XMOD Header JB?DirectionNote













Reference Designs

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In this Section you must refer to the Reference Design (Test board) for the particular module.

For Example: TE0728 Reference Designs

Notes

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In this Section you must refer to the Resources Page for the particular module.

For Example: TE0728 Resources



 


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