Page History

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ED: Tabelle ist fertig!

9) Net names for pins 4 and 5 for U11 were swapped

10) C70, C71, C72, C73, C74, C75, C76, C77, C78, C79, C80, C81, C82, C83, C84, @{"Id":"DCAOQXUV\JQHEFKQF","ObjectType":2} were added

11) R79, R80, R81, @{"Id":"DCAOQXUV\JMYBYQWI","ObjectType":2}, @{"Id":"EPHSAIGN\BPFCMKYX","ObjectType":2} were added

12) R35 was changed from 4.7k to 2.37k

13) @{"Id":"XYRRDMIL\MFKJFQBA","ObjectType":2} was changed from 4u7 6.3V 0402 to 10u 16V 0603

14) TP3 - @{"Id":"XDGVVEDM\NERJUSPY","ObjectType":2} were added

15) R25, R26, R52, R57 were changed from 4k7 to 23k7

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Changes

#1 Changed DCDC EN63A0QI (U7, U14) to LTM4638EY#PBF

Type: Schematic change

Reason: EOL of component.

Impact: None. Maximum continuous output current increased from 12A to 15A per DCDC. 

#2 Increased voltage from 1.35 V to 1.42 V via voltage divider resistor (R11) and changed voltage rail name accordingly from PL_GT_1V35 to PL_GT_1V42.

Type: Schematic Change

Reason: Improve voltage rail behaviour.

Impact: None.

#3 Changed load switch TPS27082LDDCR (Q1) to MP5077GG-Z and adapted circuit.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

#4 Changed clock (U11) from DSC1123DL5-200.0000 to SIT9121AI-2B1-XXE-200.00000

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.

Type: Schematic Change

Reason: BOM Optimization.

Impact: Decreased stability from ± 10 ppm to ± 20 ppm. Decreased temperature range from (-40 °C to 105 °C) to (-40 °C to 85 °C). Increased mechanical size.

#5 Added power supervisor STM6710LWB6F (U21) and connected it to system controller (U18) pin 5 via net "PG_ALL" which is pulled-up to power rail "3.3VIN" with resistor (R83).

Type: Schematic Change

Reason: Improve power monitoring.

Impact: Improved power monitoring circuit by supervising additional voltage rails. If monitored voltages are out of range signal "PG_ALL" is triggered.

#6 Added diode (D2) between signals "INIT_B" and "PROG_B".

Type: Schematic Change

Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

#7 Added pull-up resistor (R79, R80, R81, R82) for signals "PROG_B", "INIT_B", "DONE", "PG_GT".

Type: Schematic Change

Reason: Use external pull-up resistor.

Impact: None.

#8 Added additional decoupling capacitor (C70 ... C84, C89).

Type: Schematic Change

Reason: Improve power supply.

Impact: None.

#9

17) All SCH symbols and PCB footprints were updated from libruary

18) @{"Id":"DCAOQXUV\DXJIAUUX","ObjectType":2} was changed from 110k to 124k, net "PL_GT_1V35" was renamed to "PL_GT_1V42"

19) @{"Id":"EPHSAIGN\YARQSJWM","ObjectType":2} setted as "DNP"

Changes

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Changed ferrid bead (L1 ... L6) from BKP0603HS121-T to MPZ0603S121HT000.

Type: BOM Change

Reason:EOL of component.

Impact: None.

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#10 Changed capacitor (C49) from 4.7 µF, 6.3 V, 0402 to 10 µF 16 V, 0603.

Type:BOM Schematic Change

Reason: EOL of componentIncrease voltage rating.

Impact: None.

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#11 Changed

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resistor (R35) from 4.7 kOhm 50 mW, 0201 to 2.37 kOhm 63 mW, 0402.

Type: Schematic changeChange

Reason: EOL of componentFollow AMD recommendation.

Impact:  None. Maximum continuous output current increased from 12A to 15A per DCDC. 

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#12 Changed resistor (R25, R26, R52, R57) from 4.7 kOhm 50 mW, 0201 to 23.7 kOhm 63 mW, 0402.

Type: Schematic Change

Reason: Decrease current flow through resistor.

Impact: None.

#13 Set resistor (R71) to not fitted.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

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#14 Added testpoint (TP3 ... TP37).

Type: Schematic Change

Reason:  Keep FPGA in reset while signal "PROG_B" is low during initial power-upPower and signal monitoring improvement.

Impact: None.

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#15 Swapped clock (U11) net name "CLK200M_P" and "CLK200M_N" at pin 4 and 5.

Type: Schematic Change

Reason:Improve power monitoringDocumentation improvement.

Impact: Improved power monitoring circuit by supervising additional voltage rails. If monitored voltages are out of range signal "PG_ALL" is triggered.

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None.

#16 Updated components from library.

Type: Schematic Change

Reason: Use latest component data.

Impact: None.

#17 Signal trace lengths changed

Type: PCB change

Reason: Result of changes above.

Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0841 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#18 Added legal notices, system and power diagram. Updated revision history. Updated page count and order. 

Type: Documentation Update

Reason: Documentation improvement.

Impact: None.

#1

Type:

Reason: 

Impact:

Method of Identification

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