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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
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Overview
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CPLD Device with designator U46: 10M08SAU169
Feature Summary
- something to have access to CPLD to read out status of Power management
- Power management
- Reset
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
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Port Description
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description PCB REV04 REV05 Connection PCB REV01 REV02 Connection | ||||||||||||||||
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JTAGEN | in | E5 | -- | 3.3V | fixed to 3.3V | ||||||||||||||||
TCK_MAX10 | in | G2 | -- | 3.3V | JTAG | ||||||||||||||||
TMS_MAX10 | in | G1 | -- | 3.3V | JTAG | ||||||||||||||||
TDO_MAX10 | out | F6 | -- | 3.3V | JTAG | ||||||||||||||||
TDI_MAX10 | in | F5 | -- | 3.3V | JTAG | ||||||||||||||||
RST_EN | inout | 27 | NONE | 3.3VIN | Reset pin output to reset FPGA via CPLD chip
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EN_VTT_PL_DDR | out | J2 | 3.3V LVCMOS |
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EN_2V5_PL_DDR | out | J1 | 3.3V LVCMOS |
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EN_1V2_PL_DDR | out | H4 | 3.3V LVCMOS |
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PGPG_1V2_PL_DDR | in | H5 | 3.3V LVCMOS |
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EN_1V8_PS_AUX | out | M2 | 3.3V LVCMOS | PG_SOM | out | M1 | 3.3V LVCMOS | This pin is used as power good (input) |
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PG_SOM | out | M1 | 3.3V LVCMOS |
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PG_VCCINT | in | N3 | PG_VCCINT | N3 | 3.3V LVCMOS | LTM_FAULT | N2 | 3.3V LVCMOS | SC_EXT_2 | out | L3 | 3.3V LVCMOS | M_SDA | M3 | 3.3V LVCMOS | MR | out | K2 | 3.3V LVCMOS |
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LTM_FAULT | in | N2 | 3.3V LVCMOS |
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SC_EXT_2 | out | L3 | 3.3V LVCMOS |
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M_SDA | inout | M3 | 3.3V LVCMOS |
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MR | out | K2 | 3.3V LVCMOS |
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EN_SOM | in | K1 | 3.3V LVCMOS |
| EN_SOM | K1 | 3.3V LVCMOS|||||||||||||||
SC_EXT_3 | L2 | 3.3V LVCMOS | |||||||||||||||||||
SMB_ALERTn | L4 | 3.3V LVCMOS | |||||||||||||||||||
PG_2V5_PL_DDR | L5 | 3.3V LVCMOS | |||||||||||||||||||
EN_LTM_RUNP | out | M5 | 3.3V LVCMOS | ||||||||||||||||||
M_SCL | inout | M4 | 3.3V LVCMOS |
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nRST_SYS | K5 | 3.3V LVCMOS | |||||||||||||||||||
EN_0V9_GTH_AVCC | out | N5 | 3.3V LVCMOS | ||||||||||||||||||
EN_0V9_GTY_AVCC | out | N4 | 3.3V LVCMOS | ||||||||||||||||||
PG_1V2_PS_DDR | M7 | 3.3V LVCMOS | |||||||||||||||||||
PG_0V9_GTH_AVCC | N6 | 3.3V LVCMOS | |||||||||||||||||||
PG_0V9_GTY_AVCC | N8 | 3.3V LVCMOS | |||||||||||||||||||
EN_3V3_SW | out | N7 | 3.3V LVCMOS | ||||||||||||||||||
EN_1V2_PS_PLL | out | J6 | 3.3V LVCMOS | ||||||||||||||||||
PG_1V8_PS_GTR_AVTT | M9 | 3.3V LVCMOS | |||||||||||||||||||
PG_1V8 | M8 | 3.3V LVCMOS | |||||||||||||||||||
EN_2V5_PS_DDR | out | M13 | 3.3V LVCMOS | ||||||||||||||||||
PG_1V2_GTY_AVTT | N9 | 3.3V LVCMOS | |||||||||||||||||||
EN_1V2_GTY_AVTT | out | N10 | 3.3V LVCMOS | ||||||||||||||||||
M_INT | L11 | 3.3V LVCMOS | |||||||||||||||||||
EN_1V8_VCC_ADC | out | M11 | 3.3V LVCMOS | ||||||||||||||||||
PG_1V8_PS_GTR_AVCC | K8 | 3.3V LVCMOS | |||||||||||||||||||
EN_VTT_PS_DDR | out | J8 | 3.3V LVCMOS | ||||||||||||||||||
EN_1V8 | out | L10 | 3.3V LVCMOS | ||||||||||||||||||
EN_1V8_GTY_AUX | out | M10 | 3.3V LVCMOS | ||||||||||||||||||
PG_2V3 | N12 | 3.3V LVCMOS | |||||||||||||||||||
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EN_+1.8V_GTR_AVTT_PS | out | K10 | 3.3V LVCMOS | ||||||||||||||||||
EN_+1.8V_GTH_AUX | out | K11 | 3.3V LVCMOS | ||||||||||||||||||
EN_+1.8V_AUX | out | K12 | 3.3V LVCMOS | ||||||||||||||||||
EN_+1.2V_GTH_AVTT | out | J12 | 3.3V LVCMOS | ||||||||||||||||||
+3.3V_SW | J9 | 3.3V LVCMOS | |||||||||||||||||||
EN_+1.2V_PS_DDR | out | J13 | 3.3V LVCMOS | ||||||||||||||||||
EN_+0.85V_GTR_AVCC_PS | out | H13 | 3.3V LVCMOS | ||||||||||||||||||
PG_+1.2V_GTH_AVTT | H9 | 3.3V LVCMOS | |||||||||||||||||||
EN_VCCINT | out | H8 | 3.3V LVCMOS | ||||||||||||||||||
EN_+2.3V | out | G13 | 3.3V LVCMOS | ||||||||||||||||||
PG_+1.8V_AUX | G12 | 3.3V LVCMOS | |||||||||||||||||||
PG_2.5V_PS_DDR | L13 | 3.3V LVCMOS |
Functional Description
Power
All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.
The power-up sequence corresponds to Intel's recommendations and is shown in the table below:
Power Group | Power enable | Power good | Notes |
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0 | EN_0V9 | PG_0V9 | -- |
1 | EN_0V95 | PG_0V95 | -- |
2 | EN_1V8 | PG_1V8 | -- |
3 | EN_1V8VIO | PG_1V8VIO | -- |
EN_1V35 | PG_1V35 | -- | |
EN_VTT | -- | -- | |
VADJ_EN | PG_VADJ | 1.8V (default) | |
MAX_IO19 | MAX_IO20 | B2B J2-74/J2-76 / Signals for 3.3V on carrier board TEIB0006 → EN_3V3MB/PG_MB_3.3V | |
MAX_IO23 | MAX_IO22 | B2B J2-86/J2-82 / Signals for 1.8V on carrier board TEIB0006 → EN_1V8MB/PG_MB_1.8V |
The voltages for Bank 2K ( VCCIO2K) and Bank 2J (VCCIO2J) are supplied externally via the B2B connectors (J1-53/53 and J2-29/30).
Output voltage VADJ of power regulator U11 is set to 1.8V via VADJ_VS0 and VADJ_VS1 pin. Possible selectable voltages are 1.8V, 2.5V and 3.0V.
I2C interface
CPLD firmware consists of a i2c t GPIO block. This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20.In this case related i2c bus is bus 1.
Register | Direction in CPLD | Address |
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GPIO_input[7:0] | Output (reading from CPLD) | 0x00 |
GPIO_input[15:8] | Output (reading from CPLD) | 0x01 |
GPIO_input[23:16] | Output (reading from CPLD) | 0x02 |
GPIO_input[31:24] | Output (reading from CPLD) | 0x03 |
GPIO_output[7:0] | Input (writing to CPLD) | 0x00 |
GPIO_output[15:8] | Input (writing to CPLD) | 0x01 |
GPIO_output[23:16] | Input (writing to CPLD) | 0x02 |
GPIO_output[31:24] | Input (writing to CPLD) | 0x03 |
NOSEQ pin
This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:
NOSEQ pin as output | Condition | Command in linux console |
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'1' | GPIO_output(16) = '1' | i2cset -y 1 0x20 0x02 0x01 |
'0' | GPIO_output(16) = '0' | i2cset -y 1 0x20 0x02 0x00 |
NOSEQ pin as input | Description | Command in linux console |
Reading state of NOSEQ pin | GPIO_input(16) = NOSEQ | i2cget -y 1 0x20 0x02 |
Access to CPLD Registers
CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:
Register | Direction in CPLD | Address | Related instruction in linux console to access the register |
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GPIO_input[7:0] | Output (reading from CPLD) | 0x00 | i2cget -y 1 0x20 0x00 |
GPIO_input[15:8] | Output (reading from CPLD) | 0x01 | i2cget -y 1 0x20 0x01 |
GPIO_input[23:16] | Output (reading from CPLD) | 0x02 | i2cget -y 1 0x20 0x02 |
GPIO_input[31:24] | Output (reading from CPLD) | 0x03 | i2cget -y 1 0x20 0x03 |
GPIO_output[7:0] | Input (writing to CPLD) | 0x00 | i2cset -y 1 0x20 0x00 <data> |
GPIO_output[15:8] | Input (writing to CPLD) | 0x01 | i2cset -y 1 0x20 0x01 <data> |
GPIO_output[23:16] | Input (writing to CPLD) | 0x02 | i2cset -y 1 0x20 0x02 <data> |
GPIO_output[31:24] | Input (writing to CPLD) | 0x03 | i2cset -y 1 0x20 0x03 <data> |
Some of these registers are using to show some information same as CPLD revision and boot mode while booting.
Register | Address | related data | Read/write by user | Description |
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GPIO_input[7:0] | 0x00 | CPLD REVISION (8 bits) | No | |
GPIO_input[15:8] | 0x01 | "00" & BOOTMODE_GEN (2 bits) & PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits) | No | BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC). PUDC is the state of PUDC pin of FPGA. CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high) BOOT_MODE shows selected boot mode. |
GPIO_input8[16] | 0x02 | NOSEQ pin | Yes | |
Register | Address | related data | Description | |
GPIO_output[16] | 0x02 | NOSEQ pin | Yes |
If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:
Information | Displayed in Linux console | Description |
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CPLD Revision | CPLD_REV = <cpld revision> | |
Boot mode selection procedure | CPLD_BM = < bm selection procedure> |
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Jed file that on CPLD is programmed | BOOTMODE_GEN = < jed file type> |
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PUDC pin state | PUDC_MODE = <pudc state> |
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Boot mode | BOOT_MODE = <boot mode> |
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The CPLD revision, boot mode and other informations will be displayed while booting as shown:
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If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:
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Appx. A: Change History
For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD
Revision Changes
- REV02 to REV03
- changed top design from block design to text design
- REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV05 | REV04,REV05 |
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Appx. B: Legal Notices
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