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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

DateVersionChangesAuthor
2023-02-072.2
  • added column 'Firmware release' in 'Document Change History' table
  • changed template revision from list to table
ma
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Overview

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CPLD Device with designator U46: 10M08SAU169

Feature Summary

  • something to have access to CPLD to read out status of Power management
  • Power management
  • Reset

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

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Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank Power

Description

JTAGEN
inE5--3.3Vfixed to 3.3V
TCK_MAX10inG2--3.3VJTAG 
TMS_MAX10inG1--3.3VJTAG
TDO_MAX10outF6--3.3VJTAG 
TDI_MAX10inF5--3.3VJTAG 
 


 
EN_VTT_PL_DDRoutJ2
3.3V LVCMOS
  • Enable signal for TPS51206 (U26)
  • VTT: VTT_DDR_PL
  • VTTREF: VREFA_DDR_PL
EN_2V5_PL_DDRoutJ1
3.3V LVCMOS
  • Enable signal for TPS82130 (U22)
  • VOUT: +2.5V_PL_DDR
  • PG: PG_+2.5V_PL_DR
EN_1V2_PL_DDRoutH4
3.3V LVCMOS
  • Enable signal for TPS82130 (U24)
  • VOUT: +1.2V_PL_DDR
  • PG: PG_+1.2V_PL_DR
PG_1V2_PL_DDRinH5
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U24)
EN_1V8_PS_AUXoutM2
3.3V LVCMOS
  • Enable signal for TPS72018 (U43)
  • VOUT: +1.8V_AUX_PS
PG_SOMoutM1
3.3V LVCMOS
  • PowerGood output signal connected to J2B (D51)
  • in TEBT0865:
    • enable signal for TPS82130 (U2) → Carrier_+1.8V
    • PWRGD signal for TPS54240 (U14) → Carrier_+1.8V
PG_VCCINTinN3
3.3V LVCMOS
  • PowerGood output signal from LTM4700 (U20)
LTM_FAULTinN2
3.3V LVCMOS
  • FAULT signal from LTM4700 (U20)
SC_EXT_2outL3
3.3V LVCMOS
  • SC_EXT2 output signal connected to J2B (D52)
  • in TEBT0865:
    • enable signal for USB TPS82130 (U12)
  • Deactivated on delivery
M_SDAinoutM3
3.3V LVCMOS
  • connected to level shifter TXS0102 (U12)
  • connected to EEPROM 24AA025 (U14)
  • connected to SLS32AIA (U16)
  • connected to ATECC608B-MAH (U19)
MRoutK2
3.3V LVCMOS
  • Manual Reset 
  • actual configured as output and set to 1.
  • Should be an input for monitoring???
EN_SOMinK1
3.3V LVCMOS
  • SC_EXT4 input signal connected to J2B (D54)
  • in TEBT0865:
    • PG signal from TPS82130 (U3)→ Carrier_+1.8V
    • PWRGD signal for TPS54240 (U15)→ Carrier_+1.8V
SC_EXT_3inL2
3.3V LVCMOS
  • SC_EXT3 input signal connected to J2B (D53)
  • in TEBT0865:
    • Overcurrent Signal from TPS2051 (U9)






SMB_ALERTnin L4
3.3V LVCMOS
  • Alert signal from LTM4700 (U20)
PG_2V5_PL_DDRin L5
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U22)
EN_LTM_RUNPout
M5
3.3V LVCMOS
  • RUNP signal from LTM4700 (U20)
M_SCL inoutM4
3.3V LVCMOS
  • connected to level shifter TXS0102 (U12)
  • connected to EEPROM 24AA025 (U14)
  • connected to SLS32AIA (U16)
  • connected to ATECC608B-MAH (U19)
nRST_SYS outK5
3.3V LVCMOS
  • System reset output signal, resets eMMC, ETH-Phy and USB-Phy
EN_0V9_GTH_AVCCout
N5
3.3V LVCMOS
  • Enable signal for TPS82130 (U35)
EN_0V9_GTY_AVCCout
N4
3.3V LVCMOS
  • Enable signal for TPS82130 (U38)

PG_1V2_PS_DDR

in 
M7
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U25)

PG_0V9_GTH_AVCC

 inN6
3.3V LVCMOS
  • PowerGood output signal from LT8642 (U35)

PG_0V9_GTY_AVCC

 inN8
3.3V LVCMOS
  • PowerGood output signal from LT8642 (U38)
EN_3V3_SWout
N7
3.3V LVCMOS
  • enable signal for SIP32408 (U52)
EN_1V2_PS_PLLout
J6
3.3V LVCMOS
  • Enable signal for TPS72012 (U42)

PG_1V8_PS_GTR_AVTT

 inM9
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U47)

PG_1V8

 inM8
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U41)
EN_2V5_PS_DDRout
M13
3.3V LVCMOS
  • Enable signal for TPS82130 (U23)
PG_1V2_GTY_AVTT inN9
3.3V LVCMOS
  • PowerGood output signal from LT8642 (U39)
EN_1V2_GTY_AVTTout
N10
3.3V LVCMOS
  • Enable signal for LT8642 (U39)
M_INT L11
3.3V LVCMOS
EN_1V8_VCC_ADCout
M11
3.3V LVCMOS
  • Enable signal for TPS72018 (U49)
  • VOUT: +1.8V_VCCADC
PG_0V85_PS_GTR_AVCC inK8
3.3V LVCMOS
  • PowerGood output signal from TPS74801 (U48)
EN_VTT_PS_DDRout
J8
3.3V LVCMOS
  • Enable signal for TPS51206 (U27)
  • VTT: VTT_DDR_PS
  • VTTREF: VREFA_DDR_PS
EN_1V8out
L10
3.3V LVCMOS
  • Enable signal for TPS82130 (U41)
EN_1V8_GTY_AUXout
M10
3.3V LVCMOS
  • Enable signal for TPS72018 (U40)
  • VOUT: +1.8V_GTY_AUX
PG_2V3 inN12
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U45)

 






EN_+1.8V1V8_GTR_AVTT_PS

out
 K10
3.3V LVCMOS
  • enable signal for TPS82130 (U47)

EN_+1.8V1V8_GTH_AUX

out
 K11
3.3V LVCMOS
  • enable signal for TPS72018 (U37)
  • VOUT: +1.8V_GTH_AUX

EN_+1.8V1V8_AUX

out
K12
3.3V LVCMOS
  • enable signal for TPS82130 (U50)

EN_+1.2V1V2_GTH_AVTT

out
J12
3.3V LVCMOS
  • enable signal for LT8642 (U36)

+3.3VPG_3V3_SW

inJ9
3.3V LVCMOS
  • output voltage from secondary power SIP32408 (U52)

EN_+1.2V1V2_PS_DDR

out
J13
3.3V LVCMOS
  • enable signal for TPS82130 (U25)

EN_+0.85V0V85_GTR_AVCC_PS

out
H13
3.3V LVCMOS
  • enable signal for TPS74801 (U48)

PG_+1.2V1V2_GTH_AVTT

inH9
3.3V LVCMOS
  • PowerGood output signal from LT8642 (U36)

EN_VCCINT

out
H8
3.3V LVCMOS
  • enable signal for LTM4700 (U20)

EN_+2.3V2V3

out
G13
3.3V LVCMOS
  • enable signal for TPS82130 (U45)

PG_+1.8V1V8_AUX

inG12
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U50)

PG_2.5V2V5_PS_DDR

inL13
3.3V LVCMOS
  • PowerGood output signal from TPS82130 (U23)

Functional Description

Power

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

The power-up sequence corresponds to Intel's recommendations and is shown in the table below:

Power GroupPower enablePower goodNotes
0

EN_0V9

PG_0V9

--

1

EN_0V95

PG_0V95

--

2EN_1V8PG_1V8--
3

EN_1V8VIO

PG_1V8VIO

--

EN_1V35

PG_1V35

--

EN_VTT

--

--

VADJ_EN

PG_VADJ

1.8V (default)

MAX_IO19

MAX_IO20

B2B J2-74/J2-76 / Signals for 3.3V on carrier board TEIB0006 → EN_3V3MB/PG_MB_3.3V

MAX_IO23

MAX_IO22

B2B J2-86/J2-82 / Signals for 1.8V on carrier board TEIB0006 → EN_1V8MB/PG_MB_1.8V
(required for VCCIO voltage at Bank 2J/2K)

The voltages for Bank 2K ( VCCIO2K) and Bank 2J (VCCIO2J) are supplied externally via the B2B connectors (J1-53/53 and J2-29/30).

Output voltage VADJ of power regulator U11 is set to 1.8V via VADJ_VS0 and VADJ_VS1 pin. Possible selectable voltages are 1.8V, 2.5V and 3.0V.

I2C interface

CPLD firmware consists of a i2c t GPIO block. This subsystem provides i2c protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20.In this case related i2c bus is bus 1. 



RegisterDirection in CPLDAddress
GPIO_input[7:0]Output (reading from CPLD)0x00
GPIO_input[15:8]Output (reading from CPLD)0x01
GPIO_input[23:16]Output (reading from CPLD)0x02
GPIO_input[31:24]Output (reading from CPLD)0x03
GPIO_output[7:0]Input (writing to CPLD)0x00
GPIO_output[15:8]Input (writing to CPLD)0x01
GPIO_output[23:16]Input (writing to CPLD)0x02
GPIO_output[31:24]Input (writing to CPLD)0x03

NOSEQ pin

This pin in PCB REV04 with old CPLD firmware version (REV04) is  used as boot mode pin select. If  CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and  NOSEQ is  high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:

NOSEQ pin as outputConditionCommand in linux console
'1'GPIO_output(16) = '1'
i2cset -y 1 0x20 0x02 0x01
'0'GPIO_output(16) = '0'
i2cset -y 1 0x20 0x02 0x00
NOSEQ pin as inputDescriptionCommand in linux console
Reading state of NOSEQ pinGPIO_input(16) = NOSEQ
i2cget -y 1 0x20 0x02


Access to CPLD Registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

RegisterDirection in CPLDAddressRelated instruction in linux console to access the register
GPIO_input[7:0]Output (reading from CPLD)0x00i2cget -y 1 0x20 0x00
GPIO_input[15:8]Output (reading from CPLD)0x01i2cget -y 1 0x20 0x01
GPIO_input[23:16]Output (reading from CPLD)0x02i2cget -y 1 0x20 0x02
GPIO_input[31:24]Output (reading from CPLD)0x03i2cget -y 1 0x20 0x03
GPIO_output[7:0]Input (writing to CPLD)0x00i2cset -y 1 0x20 0x00 <data>
GPIO_output[15:8]Input (writing to CPLD)0x01i2cset -y 1 0x20 0x01 <data>
GPIO_output[23:16]Input (writing to CPLD)0x02i2cset -y 1 0x20 0x02 <data>
GPIO_output[31:24]Input (writing to CPLD)0x03

i2cset -y 1 0x20 0x03 <data>

Some of these registers are using to show some information same as  CPLD revision and boot mode while booting.

RegisterAddressrelated  dataRead/write by userDescription
GPIO_input[7:0]0x00CPLD REVISION (8 bits)No
GPIO_input[15:8]0x01"00" & BOOTMODE_GEN (2 bits) &  PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits)No

BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).

PUDC is the state of PUDC pin of FPGA.

CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)

BOOT_MODE shows selected boot mode.

GPIO_input8[16]0x02NOSEQ pinYes
RegisterAddressrelated data
Description
GPIO_output[16]0x02NOSEQ pinYes

If CPLD firmware version is  REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code  while booting. The format of these informations are shown in the following:

InformationDisplayed in Linux consoleDescription
CPLD RevisionCPLD_REV = <cpld revision>
Boot mode selection procedureCPLD_BM = < bm selection procedure>
  • If boot mode via hardware is selected → Deactive(0)
  • If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
Jed file that on CPLD is programmedBOOTMODE_GEN = < jed file type>
  • Jed file type can be one of the following types :
    • (0) QSPI/SD
    • (1) QSPI/JTAG
    • (2) JTAG/SD
    • (3) default QSPI/JTAG/SD/eMMC
PUDC pin statePUDC_MODE = <pudc state>
  • PUDC can have one of the following state:
    • Pull-up activated (0)
    • Pull-up deactivated (1)
Boot modeBOOT_MODE = <boot mode>
  • The following boot modes can displayed:
    • eMMC (0)
    • JTAG (1)
    • QSPI (2)
    • SD Card (3)

The CPLD revision, boot mode and other informations will be displayed while booting as shown:

Scroll Title
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titleAll information while booting

If PCB revision is REV04 and  CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as  boot mode while booting and the following message will be displayed:

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titleMessage while booting if CPLD firmware version is old for PCB REV04


Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

  • REV02 to REV03
    • changed top design from block design to text design
  • REV01 to REV02
    • added Pin L3 SC_EXT_2 as output and set to VCC to enable USB

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

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REV05REV04,REV05
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Appx. B: Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices



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