Page History
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Impact: DDR timing needs to be considered in customer design. Trenz Reference Design reflects it without changing timing but custom firmware needs to be checked and eventually updated by customer.
#2 Changed DDR4 SDRAM (U2, U3) from K4AAG165WB-MCRC0CV to MT40A1G16TB-062E IT:F, set termination resistor (R94) from fitted to not fitted, and change resistor (R68, R69) from 240 Ohm to 0 Ohm.
Type: BOM change
Reason: BOM Optimization.
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Impact: Customer system power sequencing needs to be checked/adapted according to new module power sequencing.
#4.1 Enable DCDC (U12) via net "EN".
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.2 Enable DCDC (U27) via net "PG_0V85".
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.
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3 Changed DCDC (U20) power-up from net "PG_0V85" to "PG_PSLP_INTIO". DCDC (U27) enables DCDC (U20).
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.
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4 Changed power sequence: DCDC (U26) enables DCDC (U4, U23) via net "PG_FP0V85".
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.
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5 Changed power sequence: DCDC (U4) enables DCDC (U9) via net "PG_DDR2V5".
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.
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6 Changed resistor (R70) functionality from pull-up resistor for DCDC (U9) to pull-up resistor for DCDC (U26).
Type: Schematic Change
Reason: Refer to #4.
Impact: Refer to #4.
#4.
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7 Added pull-up resistor (R122).
Type: Schematic Change
Reason: Refer to #4.
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Reason: Enable DDR4 test improvement.
Impact: None.
#13 Connect SoC (U1) bank 64 IO pins and VCCO pins together to net "GND".
Type: Schematic Change
Reason: Improvement ESD protection.
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Reason: BOM Optimization.
Impact: None.
#19 Changed capacitor (C12, C13, C14, C15, C16, C45, C49, C52, C53, C57) from 4.7 µF, 6.3 V, to 10 µF, 10 V.
Type: Schematic Change
Reason: AMD recommendation.
Impact: None.
#20 Changed 10 µF capacitor (C2, C37, C41, C48, C89, C94, C95,
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C107, C130,
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C132, C134) from 16 V, 0603 to 10 V, 0402.
Type: Schematic Change
Reason: BOM Optimization.
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Reason: BOM Optimization.
Impact: None.
#22 Changed capacitor (C136, C140) from 22 µF
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to 47 µF.
Type: Schematic Change
Reason: AMD recommendation.
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#23 Changed 47 µF capacitor (C24, C25, C96, C110) from 0805 to 0603.
Type: Schematic Change
Reason: BOM Optimization.
Impact: None.
#25 Changed ferrid bead (L1, L2, L3, L5, L7, L9, L10, L11, L12) from BKP0603HS121-T to MPZ0603S121HT000.
Type: BOM Change
Reason:EOL of component.
Impact: None.
#25 Changed 10 kOhm resistor (R36, R51, R87) from 50 mW, 0201 to 63 mW, 0402.
Type: BOM Change
Reason:BOM Optimization.
Impact: None.
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Reason: Documentation Improvement
Impact: None.
#25 Added testpoints (TP18, TP21, TP22, TP23, TP24, TP25).
Type: Schematic Change
Reason: Improve voltage measuring possibilities.
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