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Affected Product

Changes

Replacement
TE0821-01-3BE21MA#1, #3 ... #?#30TE0821-02-3BE81MA
TE0821-01-3BE21MC#1, #3 ... #?#30TE0821-02-3BE81MC
TE0821-01-3BE21ML#1, #3 ... #?#30TE0821-02-3BE81ML
TE0821-01-3BI21MA#1, #3 ... #?#30TE0821-02-3BI81MA
TE0821-01-4DE31ML#2 ... #?#30TE0821-02-4DE91ML
TE0821-01-2AE31PA#2 ... #?#30TE0821-02-2AE91PA
TE0821-01-3AE31PA#2 ... #?#30TE0821-02-3AE91PA
TE0821-01-3BI91ND#3 ... #?#30TE0821-02-3BI91ND

ED: Tablle ist fertig!

Changes

#1 Changed DDR4 SDRAM (U2, U3) from K4A8G165WB-BIRC to K4A8G165WC-BITDTCV.

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Impact:  DDR timing needs to be considered in customer design. Trenz Reference Design reflects it without changing timing but custom firmware needs to be checked and eventually updated by customer.

#2 Changed DDR4 SDRAM (U2, U3) from K4AAG165WB-MCRC0CV to MT40A1G16TB-062E IT:F, set termination resistor (R94) from fitted to not fitted, and

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changed resistor (R68, R69) from 240 Ohm to 0 Ohm.

Type: BOM change

Reason: BOM Optimization.

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Reason: Improved SPI interface usage with different flashs.

Impact: None.

#17

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Added additional decoupling capacitor (C144, C178, C186

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... C189).

Type: Schematic Change

Reason: Improve power supply decoupling.

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Reason: BOM Optimization.

Impact: None.

#19 Changed capacitor (C12

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... C16, C45, C49, C52, C53, C57) from 4.7 µF, 6.3 V, to 10 µF, 10 V.

Type: Schematic Change

Reason: AMD recommendation.

Impact: None.

#20 Changed 10 µF capacitor (C2,

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C18, C20, C22, C37, C41, C48,

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C82, C89, C92, C94,

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 C95, C107, C130, C132, C134) from 16 V, 0603 to 10 V, 0402.

Type: Schematic Change

Reason: BOM Optimization.

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Reason: AMD recommendation.

Impact: None.

#23 Changed 47 µF capacitor (C24, C25, C27, C33, C34, C88, C96, C110) from 0805 to 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

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#24 Changed ferrid bead (L1

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... L3, L5, L7, L9

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... L12)

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from BKP0603HS121-T to MPZ0603S121HT000.

Type: BOM Change

Reason:EOL of component.

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Reason:BOM Optimization.

Impact: None.

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#26 Changed net "PG_PS_LP" to "PG_PSLP_INTIO", net "PS_AVCC" to "PS_MGTRAVCC", net "PG_AVCC" to "PG_MGTRAVCC", net "OTG_RCLK" to "OTG_REFCLK", net "PS_AVTT" to "PS_MGTRAVTT", and net "PG_DDR" to "PG_DDR1V2".

Type: Schematic Change

Reason: Documentation Improvement 

Impact: None.

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#27 Added testpoints (TP18, TP21

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... TP25).

Type: Schematic Change

Reason:Improve voltage measuring possibilities Voltage and system monitoring improvement.

Impact: None.

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#28 Changed signal trace lengths.

Type: PCB Change

Reason: Result of changes above.

Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0821 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#29 Updated "FPGA Speed grade" information table on page "TE0821 - POWER".

Type: Documentation Update

Reason: Documentation Improvement

Impact: None.

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#30 Added power diagram. Updated system overview and revision history. Updated page count and order. 

Type: Documentation Update

Reason: Documentation improvementImprovement.

Impact: None.

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Method of Identification

The revision number is shown on the top side of the PCB.

Image Added

Production Shipment Schedule

From XXXXXJanuary 2025, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

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Contact Information

If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at

Disclaimer

Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances.  For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.

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