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ILA Core NameSample RateDepthConnection
xmod_uart10MHz10 MS/s128KUART RXD in XMOD connector
POF375MHz1 GS/s4K128KLVDS input from POF fibre receiver
J1_J2100MHz100 MS/s4KJ1: 42 pins, J2: 42 pins

Sample depths can be increased for all modules with FPGA's larger than A15T.

Channel NameMeasurement TypeConnection
CFCLKFrequencyFree running configuration clock, nominal 66MHz
J1_FREQFrequencyinput multiplexer, from any pin in J1
J1_DUTYDuty Cycleinput multiplexer, from any pin in J1
J2_FREQFrequencyinput multiplexer, from any pin in J2
J2_DUTYDuty Cycleinput multiplexer, from any pin in J2
POF_FREQFrequencyLVDS input from POF receiver
POF_DUTYDuty CycleLVDS input from POF receiver

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