Page History

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Products Affected

This change affects all Trenz Electronic TE0821 SoMs: TE0821-01*.

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Impact: Module reset, enable, and power-up handling is modified. That means that "EN" signal from B2B connector enables DCDC U5 and DCDC U12 and can be monitored by CPLD U21 pin 27 (assembly option) (backward compatible mode with assembled resistor R113 and signal "EN" as enable input), or that signal "EN" Two different options are possible: (1) Standard option: Signal "EN" only enables DCDC U5 and DCDC U12 and CPLD U21 pin 27 is connected to signal "POR_B" via voltage translator T2; (normal mode). Normal mode is standard. 2) Backwards compatible option: "EN" signal from B2B connector enables DCDC U5 and DCDC U12 and can be monitored by CPLD U21 pin 27; Therefore, please, verify that the module meets your requierements.

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Type: Schematic Change

Reason: Orientate towards Follow (more closely) AMD recommended power sequence.

Impact: Customer system power sequencing needs to be checked/adapted according to new module power sequencing Sequence of external (B2B) available power rails is not changed. A slightly enlarged time constant between "EN" high and power up of 1.8V rail could be observed.

#4.1 Enable DCDC (U12) via net "EN".

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Impact: Improved power monitoring circuit by supervising additional voltage rails. If monitored voltages are out of range signal "PG_ALL" is triggereddeasserted.

#9 Removed pull-up resistor (R82) from signal "MR".

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Reason: Use internal pull-up resistor.

Impact: None.

#10

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Added capacitor (C143) for signal "MR".

Type: Schematic Change

Reason: Improve noise immunity.

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Reason: Enable DDR4 test improvement.

Impact: None.

#13

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Connected unused SoC (U1) bank 64 IO pins and VCCO pins together to net "GND".

Type: Schematic Change

Reason: Improvement ESD protection.

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Type: Schematic Change

Reason: Improvement Add feature to allow "POR_OVERRIDE" state changeassembly options with POR Override "high".

Impact: None. Assembly option with power override possible.

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Reason:BOM Optimization.

Impact: None.

#26 Changed net names "PG_PS_LP" to "PG_PSLP_INTIO",

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"PS_AVCC" to "PS_MGTRAVCC",

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"PG_AVCC" to "PG_MGTRAVCC",

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"OTG_RCLK" to "OTG_REFCLK",

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"PS_AVTT" to "PS_MGTRAVTT", and

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"PG_DDR" to "PG_DDR1V2".

Type: Schematic Change

Reason: Documentation Improvement 

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Production Shipment Schedule

From January February 2025, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

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