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This one of easiest solutions to implement full multiboot application for any Xilinx 7 Series or Ultrascale FPGA.
A Microblaze based system should be made with following IP Core from Xilinx free Vivado IP Catalog:
- AXI QSPI
- AXI_HWICAP
- AXI_UARTLITE
- AXI_GPIO
- MIG (for External Memory access)
| Offset | Size | Content | Notes |
|---|---|---|---|
| Application bitstream #2 | |||
| Application bitstream #2 | |||
| u-boot converted to SREC format | |||
| 0x2000 | u-boot flash environment | ||
| 0x000000 | GOLDEN bitstream with SREC Loader |
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