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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

Date	Version	Changes	Author
2023-02-07	2.2	added column 'Firmware release' in 'Document Change History' table changed template revision from list to table	ma
-	2.1	Fix problem with pdf export and side scroll bar	-
-	2.0	add fix table of content add table size as macro removed page initial creator	-

Overview

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CPLD Device with designator U46: 10M08SAU169

Feature Summary

something to have access to CPLD to read out status of Power management
Power management
Reset

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

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Port Description

)in TEBT0865:PG signal from TPS82130 (U3→ Carrier_+1.8V

PWRGD signal for TPS54240 (U15)→ Carrier_+1.8V

)PWRGD

Name / opt. VHD Name	Direction	Pin	I/O Bank	Pullup/Down	I/O Standard	Current Strength	Description
JTAGEN	in	E5		--	3.3V		fixed to 3.3V
TCK_MAX10	in	G2		--	3.3V		JTAG
TMS_MAX10	in	G1		--	3.3V		JTAG
TDO_MAX10	out	F6		--	3.3V		JTAG
TDI_MAX10	in	F5		--	3.3V		JTAG

PG_1V2_PL_DDR	in	H5	2	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U24) open drain output, pull-up resistor needed EN: EN_+1.2V_PL_DDR VOUT: +1.2V_PL_DDR
PG_VCCINT	in	N3	2	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from LTM4700 (U20) open drain output, pull-up resistor needed
LTM_FAULT	in	N2	2		3.3V LVCMOS	2mA (default)	FAULT signal from LTM4700 (U20) open drain input and output, pull-up resistor needed
M_SDA	inout	M3	2		3.3V LVCMOS	2mA (default)	connected to level shifter TXS0102 (U12) connected to EEPROM 24AA025 (U14) connected to SLS32AIA (U16) connected to ATECC608B-MAH (U19) connected to LTM4700 (U20) open drain input and output, pull-up resistor needed
EN_SOM	in	K1	2	weak pull-up	3.3V LVCMOS	2mA (default)	SC_EXT4 input signal connected to J2B (D54	)
SC_EXT_3	in	L2	2		3.3V LVCMOS	2mA (default)	SC_EXT3 input signal connected to J2B (D53) in TEBT0865: Overcurrent Signal from TPS2051 (U9	) open drain output, active low
EN_VTT_PL_DDR	out	J2	2		3.3V LVTTL	8mA (default)	Enable signal for TPS51206 (U26) VTT: VTT_DDR_PL VTTREF: VREFA_DDR_PL
EN_2V5_PL_DDR	out	J1	2		3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U22) VOUT: +2.5V_PL_DDR PG: PG_+2.5V_PL_DR
EN_1V2_PL_DDR	out	H4	2		3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U24) VOUT: +1.2V_PL_DDR PG: PG_+1.2V_PL_DR
EN_1V8_PS_AUX	out	M2	2		3.3V LVTTL	8mA (default)	Enable signal for TPS72018 (U43) VOUT: +1.8V_AUX_PS
PG_SOM	out	M1	2		3.3V LVTTL	8mA (default)	PowerGood output signal connected to J2B (D51) in TEBT0865: enable signal for TPS82130 (U2) → Carrier_+1.8V	enable signal for TPS54240 (U14) → Carrier_+1.8V
SC_EXT_2	out	L3	2		3.3V LVTTL	8mA (default)	SC_EXT2 output signal connected to J2B (D52) in TEBT0865: enable signal for USB TPS82130 (U12) Deactivated on delivery
MR	out	K2	2		3.3V LVCMOS	2mA (default)	Manual Reset actual configured as output and set to 1. Should be an input for monitoring???



SMB_ALERTn	in	L4			3.3V LVCMOS	2mA (default)	Alert signal from LTM4700 (U20) open drain output, pull-up resistor needed
PG_2V5_PL_DDR	in	L5		weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U22) open drain output, pull-up resistor needed EN: EN_+2.5V_PL_DDR VOUT: +2.5V_PL_DDR
EN_LTM_RUNP	out	M5			3.3V LVCMOS	2mA (default)	RUNP signal from LTM4700 (U20) enables board bias circuit to supply IC and to drive the MOSFET when the SVin is higher than 7V. Needs to be '1' ; Tie to ground to disable the bias circuit when Vin is less than 5,75V
M_SCL	inout	M4			3.3V LVCMOS	2mA (default)	connected to level shifter TXS0102 (U12) connected to EEPROM 24AA025 (U14) connected to SLS32AIA (U16) connected to ATECC608B-MAH (U19) connected to LTM4700 (U20) open drain input and output, pull-up resistor needed
nRST_SYS	out	K5			3.3V LVCMOS		System reset output signal, resets eMMC, ETH-Phy and USB-Phy
EN_0V9_GTH_AVCC	out	N5			3.3V LVCMOS		Enable signal for TPS82130 (U35)
EN_0V9_GTY_AVCC	out	N4			3.3V LVCMOS		Enable signal for TPS82130 (U38)
PG_1V2_PS_DDR	in	M7		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U25)
PG_0V9_GTH_AVCC	in	N6			3.3V LVCMOS		PowerGood output signal from LT8642 (U35)
PG_0V9_GTY_AVCC	in	N8			3.3V LVCMOS		PowerGood output signal from LT8642 (U38)
EN_3V3_SW	out	N7			3.3V LVCMOS		enable signal for SIP32408 (U52)
EN_1V2_PS_PLL	out	J6			3.3V LVCMOS		Enable signal for TPS72012 (U42)
PG_1V8_PS_GTR_AVTT	in	M9		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U47)
PG_1V8	in	M8		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U41)
EN_2V5_PS_DDR	out	M13			3.3V LVCMOS		Enable signal for TPS82130 (U23)
PG_1V2_GTY_AVTT	in	N9		weak pull-up	3.3V LVCMOS		PowerGood output signal from LT8642 (U39)
EN_1V2_GTY_AVTT	out	N10			3.3V LVCMOS		Enable signal for LT8642 (U39)
M_INT		L11			3.3V LVCMOS
EN_1V8_VCC_ADC	out	M11			3.3V LVCMOS		Enable signal for TPS72018 (U49) VOUT: +1.8V_VCCADC
PG_0V85_PS_GTR_AVCC	in	K8		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS74801 (U48)
EN_VTT_PS_DDR	out	J8			3.3V LVCMOS		Enable signal for TPS51206 (U27) VTT: VTT_DDR_PS VTTREF: VREFA_DDR_PS
EN_1V8	out	L10			3.3V LVCMOS		Enable signal for TPS82130 (U41)
EN_1V8_GTY_AUX	out	M10			3.3V LVCMOS		Enable signal for TPS72018 (U40) VOUT: +1.8V_GTY_AUX
PG_2V3	in	N12		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U45)

EN_1V8_GTR_AVTT_PS	out	K10			3.3V LVCMOS		enable signal for TPS82130 (U47)
EN_1V8_GTH_AUX	out	K11			3.3V LVCMOS		enable signal for TPS72018 (U37) VOUT: +1.8V_GTH_AUX
EN_1V8_AUX	out	K12			3.3V LVCMOS		enable signal for TPS82130 (U50)
EN_1V2_GTH_AVTT	out	J12			3.3V LVCMOS		enable signal for LT8642 (U36)
PG_3V3_SW	in	J9			3.3V LVCMOS		output voltage from secondary power SIP32408 (U52)
EN_1V2_PS_DDR	out	J13			3.3V LVCMOS		enable signal for TPS82130 (U25)
EN_0V85_GTR_AVCC_PS	out	H13			3.3V LVCMOS		enable signal for TPS74801 (U48)
PG_1V2_GTH_AVTT	in	H9		weak pull-up	3.3V LVCMOS		PowerGood output signal from LT8642 (U36)
EN_VCCINT	out	H8			3.3V LVCMOS		enable signal for LTM4700 (U20)
EN_2V3	out	G13			3.3V LVCMOS		enable signal for TPS82130 (U45)
PG_1V8_AUX	in	G12		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U50)
PG_2V5_PS_DDR	in	L13		weak pull-up	3.3V LVCMOS		PowerGood output signal from TPS82130 (U23)

Functional Description

Power

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

The power-up sequence corresponds to AMD's recommendations and is shown in the table below:

Power Group	Power enable signal (CPLD output signal)	Power good signal (CPLD input signal)	Notes
0	--	EN_SOM
1	EN_VCCINT	PG_VCCINT	--
	EN_2V3	PG_2V3	--
	EN_3V3_SW	PG_3V3_SW	+3.3V_SW output signal from U52
2	EN_1V8	PG_1V8	--
	EN_1V8_AUX	PG_1V8_AUX	--
	EN_1V8_PS_AUX	--	--
	EN_1V2_PS_PLL	--	--
	EN_0V9_GTH_AVCC	PG_0V9_GTH_AVCC	--
	EN_0V9_GTY_AVCC	PG_0V9_GTY_AVCC	--
	EN_1V8_VCC_ADC	--	--
3	EN_1V2_PS_DDR	PG_1V2_PS_DDR	--
	EN_1V2_PL_DDR	PG_1V2_PL_DDR	--
	EN_2V5_PL_DDR	PG_2V5_PL_DDR	--
	EN_2V5_PS_DDR	PG_2V5_PS_DDR	--
	EN_1V2_GTH_AVTT	PG_1V2_GTH_AVTT	--
	EN_1V2_GTY_AVTT	PG_1V2_GTY_AVTT	--
4	EN_VTT_PS_DDR	--	--
	EN_0V85_PS_GTR_AVCC	PG_0V85_PS_GTR_AVCC	--
	EN_VTT_PL_DDR	--	--
	EN_1V8_GTH_AUX	--	--
	EN_1V8_GTY_AUX	--	--
5	EN_1V8_PS_GTR_AVTT	PG_1V8_PS_GTR_AVTT	--
6	PG_SOM	--	--

Power Group	Power enable signal (CPLD output signal)	Power good signal (CPLD input signal)	Notes
0	--	EN_SOM
1	EN_VCCINT	PG_VCCINT	--
	EN_2V3	PG_2V3	--
	EN_3V3_SW	PG_3V3_SW	+3.3V_SW output signal from U52
2	EN_1V8	PG_1V8	--
	EN_1V8_AUX	PG_1V8_AUX	--
	EN_1V8_PS_AUX	--	--
	EN_1V2_PS_PLL	--	--
	EN_0V9_GTH_AVCC	PG_0V9_GTH_AVCC	--
	EN_0V9_GTY_AVCC	PG_0V9_GTY_AVCC	--
	EN_1V8_VCC_ADC	--	--
3	EN_1V2_PS_DDR	PG_1V2_PS_DDR	--
	EN_1V2_PL_DDR	PG_1V2_PL_DDR	--
	EN_1V2_GTH_AVTT	PG_1V2_GTH_AVTT	--
	EN_1V2_GTY_AVTT	PG_1V2_GTY_AVTT	--
4	EN_VTT_PS_DDR	--	--
	EN_0V85_PS_GTR_AVCC	PG_0V85_PS_GTR_AVCC	--
	EN_VTT_PL_DDR	--	--
	EN_2V5_PL_DDR	PG_2V5_PL_DDR	--
	EN_2V5_PS_DDR	PG_2V5_PS_DDR	--
	EN_1V8_GTH_AUX	--	--
	EN_1V8_GTY_AUX	--	--
5	EN_1V8_PS_GTR_AVTT	PG_1V8_PS_GTR_AVTT	--
6	PG_SOM	--	--

JTAG UART

As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.

The command "nios2-terminal.exe" in the NIOS II command shell is used to output the power good signals and the revision of the CPLD firmware and the PCB.

I2C interface

CPLD firmware consists of an I2C Slave to Avalon-MM Master Bridge Intel FPGA IP i2c t GPIO block. This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20. In this case related i2c bus is bus 1.

Register	Direction in CPLD	Address
GPIO_input[7:0]	Output (reading from CPLD)	0x00
GPIO_input[15:8]	Output (reading from CPLD)	0x01
GPIO_input[23:16]	Output (reading from CPLD)	0x02
GPIO_input[31:24]	Output (reading from CPLD)	0x03
GPIO_output[7:0]	Input (writing to CPLD)	0x00
GPIO_output[15:8]	Input (writing to CPLD)	0x01
GPIO_output[23:16]	Input (writing to CPLD)	0x02
GPIO_output[31:24]	Input (writing to CPLD)	0x03

NOSEQ pin

This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:

NOSEQ pin as output	Condition	Command in linux console
'1'	GPIO_output(16) = '1'	i2cset -y 1 0x20 0x02 0x01
'0'	GPIO_output(16) = '0'	i2cset -y 1 0x20 0x02 0x00
NOSEQ pin as input	Description	Command in linux console
Reading state of NOSEQ pin	GPIO_input(16) = NOSEQ	i2cget -y 1 0x20 0x02

Access to CPLD Registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

Register Address	Direction in CPLD	Related instruction in linux console to access the register
0x00	Output (reading from CPLD)	i2cget -y 1 0x20 0x00
0x01	Output (reading from CPLD)	i2cget -y 1 0x20 0x01
0x0C	Input (writing to CPLD)	i2cset -y 1 0x20 0x00 <data>
GPIO_output[15:8]	Input (writing to CPLD)	i2cset -y 1 0x20 0x01 <data>
GPIO_output[23:16]	Input (writing to CPLD)	i2cset -y 1 0x20 0x02 <data>
GPIO_output[31:24]	Input (writing to CPLD)	i2cset -y 1 0x20 0x03 <data>

Some of these registers are using to show some information same as CPLD revision and boot mode while booting.

Register	Address	related data	Read/write by user	Description
GPIO_input[7:0]	0x00	CPLD REVISION (8 bits)	No
GPIO_input[15:8]	0x01	"00" & BOOTMODE_GEN (2 bits) & PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits)	No	BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC). PUDC is the state of PUDC pin of FPGA. CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high) BOOT_MODE shows selected boot mode.
GPIO_input8[16]	0x02	NOSEQ pin	Yes
Register	Address	related data		Description
GPIO_output[16]	0x02	NOSEQ pin	Yes

If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:

Information	Displayed in Linux console	Description
CPLD Revision	CPLD_REV = <cpld revision>
Boot mode selection procedure	CPLD_BM = < bm selection procedure>	If boot mode via hardware is selected → Deactive(0) If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
Jed file that on CPLD is programmed	BOOTMODE_GEN = < jed file type>	Jed file type can be one of the following types : (0) QSPI/SD (1) QSPI/JTAG (2) JTAG/SD (3) default QSPI/JTAG/SD/eMMC
PUDC pin state	PUDC_MODE = <pudc state>	PUDC can have one of the following state: Pull-up activated (0) Pull-up deactivated (1)
Boot mode	BOOT_MODE = <boot mode>	The following boot modes can displayed: eMMC (0) JTAG (1) QSPI (2) SD Card (3)

The CPLD revision, boot mode and other informations will be displayed while booting as shown:

Scroll Title

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title	All information while booting

If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:

Scroll Title

title-alignment	center
title	Message while booting if CPLD firmware version is old for PCB REV04

Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

REV02 to REV03
- changed top design from block design to text design
REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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	current-version
	current-version
prefix	v.

REV03

REV02

Page info

	modified-user
	modified-user

All

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	modified-users
	modified-users

Appx. B: Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

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Old Version 17

New Version 18

Key

Overview

Feature Summary

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

Power

JTAG UART

I2C interface

NOSEQ pin

Access to CPLD Registers

Appx. A: Change History

Revision Changes

Document Change History

Appx. B: Legal Notices

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