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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"
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Overview
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CPLD Device with designator U46: 10M08SAU169
Feature Summary
- JTAG_UART
- Power management
- Reset
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
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Port Description
Name / opt. VHD Name | Direction | Pin | I/O Bank | Pullup/Down | I/O Standard | Current Strength | Description |
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JTAGEN | in | E5 | -- | 3.3V | fixed to 3.3V | ||
TCK_MAX10 | in | G2 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TMS_MAX10 | in | G1 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TDO_MAX10 | out | F6 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TDI_MAX10 | in | F5 | -- | 2.5V (default) | 12mA (default) | JTAG | |
PG_1V2_PL_DDR | in | H5 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_VCCINT | in | N3 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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LTM_FAULT | in | N2 | 2 | 3.3V LVCMOS | 2mA (default) |
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M_SDA | inout | M3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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EN_SOM | in | K1 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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SC_EXT_3 | in | L2 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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EN_VTT_PL_DDR | out | J2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_2V5_PL_DDR | out | J1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PL_DDR | out | H4 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_PS_AUX | out | M2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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PG_SOM | out | M1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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SC_EXT_2 | out | L3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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MR | inout | K2 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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SMB_ALERTn | in | L4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_2V5_PL_DDR | in | L5 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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M_SCL | inout | M4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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nRST_SYS | out | K5 | 3 | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_PS_DDR | in | M7 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_0V9_GTH_AVCC | in | N6 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_0V9_GTY_AVCC | in | N8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8_PS_GTR_AVTT | in | M9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8 | in | M8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_GTY_AVTT | in | N9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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M_INT | in | L11 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_0V85_PS_GTR_AVCC | in | K8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_2V3 | in | N12 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_LTM_RUNP | out | M5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V9_GTH_AVCC | out | N5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V9_GTY_AVCC | out | N4 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_3V3_SW | out | N7 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PS_PLL | out | J6 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_2V5_PS_DDR | out | M13 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_GTY_AVTT | out | N10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_VCC_ADC | out | M11 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_VTT_PS_DDR | out | J8 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8 | out | L10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_GTY_AUX | out | M10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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PG_3V3_SW | in | J9 | 5 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_GTH_AVTT | in | H9 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8_AUX | in | G12 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_2V5_PS_DDR | in | L13 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_1V8_PS_GTR_AVTT | out | K10 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_GTH_AUX | out | K11 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_AUX | out | K12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_GTH_AVTT | out | J12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PS_DDR | out | J13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V85_PS_GTR_AVCC | out | H13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_VCCINT | inout | H8 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_2V3 | out | G13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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Functional Description
JTAG
JTAG access to Intel MAX 10 is available through B2B connector J2.
JTAG Signal | B2B Connector |
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JTAGEN | Pulled Up |
TCK_MAX10 | J2B- D56 |
TDI_MAX10 | J2B- D59 |
TDO_MAX10 | J2B- D58 |
TMS_MAX10 | J2B- D57 |
Power
All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals. As the power good inputs of the power sequencer are very sensitive, all power good inputs were debounced.
The power-up sequence corresponds to AMD's recommendations and is shown in the table below:
Power Group | Power enable signal (CPLD output signal) | Power good signal (CPLD input signal) | Notes |
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0 | -- | EN_SOM |
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1 | EN_VCCINT | PG_VCCINT | -- |
EN_2V3 | PG_2V3 | -- | |
EN_3V3_SW | PG_3V3_SW | +3.3V_SW output signal from U52 | |
2 | EN_1V8 | PG_1V8 | -- |
EN_1V8_AUX | PG_1V8_AUX | -- | |
EN_1V8_PS_AUX | -- | -- | |
EN_1V2_PS_PLL | -- | -- | |
EN_0V9_GTH_AVCC | PG_0V9_GTH_AVCC | -- | |
EN_0V9_GTY_AVCC | PG_0V9_GTY_AVCC | -- | |
EN_1V8_VCC_ADC | -- | -- | |
3 | EN_1V2_PS_DDR | PG_1V2_PS_DDR | -- |
EN_1V2_PL_DDR | PG_1V2_PL_DDR | -- | |
EN_2V5_PL_DDR | PG_2V5_PL_DDR | -- | |
EN_2V5_PS_DDR | PG_2V5_PS_DDR | -- | |
EN_1V2_GTH_AVTT | PG_1V2_GTH_AVTT | -- | |
EN_1V2_GTY_AVTT | PG_1V2_GTY_AVTT | -- | |
4
| EN_VTT_PS_DDR | -- | -- |
EN_0V85_PS_GTR_AVCC | PG_0V85_PS_GTR_AVCC | -- | |
EN_VTT_PL_DDR | -- | -- | |
EN_1V8_GTH_AUX | -- | -- | |
EN_1V8_GTY_AUX | -- | -- | |
5 | EN_1V8_PS_GTR_AVTT | PG_1V8_PS_GTR_AVTT | -- |
6 | PG_SOM | -- | -- |
JTAG UART
As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.
The command "nios2-terminal.exe" in the NIOS II command shell is used to output the CPLD Firmware and PCB revision. In case of power problems the power enable and power good signals will be displayed additionally.
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see also https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/jtag-uart-core.html
I2C interface
CPLD firmware consists of an I2C Slave to Avalon-MM Master Bridge Intel FPGA IP i2c t GPIO block . This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20. In this case related i2c bus is bus 1.
Index | Byte | Register | Direction in CPLD | Address | Name | Read/Write | Description | Default |
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0x0 | GPIO_input[7:0] | Output (reading from CPLD) | 0x00 | |||||
GPIO_input[15:8] | Output (reading from CPLD) | 0x01 | ||||||
GPIO_input[23:16] | Output (reading from CPLD) | 0x02 | ||||||
GPIO_input[31:24] | Output (reading from CPLD) | 0x03 | ||||||
GPIO_output[7:0] | Input (writing to CPLD) | 0x00 | ||||||
GPIO_output[15:8] | Input (writing to CPLD) | 0x01 | ||||||
GPIO_output[23:16] | Input (writing to CPLD) | 0x02 | ||||||
GPIO_output[31:24] | Input (writing to CPLD) | 0x03 |
NOSEQ pin
This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:
i2cset -y 1 0x20 0x02 0x01
i2cset -y 1 0x20 0x02 0x00
i2cget -y 1 0x20 0x02
SC_REVISION | R | CPLD Firmware Revision | 0x3 | ||
0x1 | [7:0] | PCB_REVISION | R | PCB Revision | 0x2 |
0x6 | [7:0] | pwr_en | R | Status of Power Groups
| 0x7F |
0x8 | [7:0] | power_good_in[7:0] | R | Status of Power Good Signals | 0xFF |
0x9 | [7:0] | power_good_in[15:8] | R | Status of Power Good Signals | 0xFF |
0xA | [7:0] | seq_nfault | R | Status of Power Sequencer | 0x1 |
0xE | [7:0] | pwr_usb_ena | R/W | Enables/Disables output signal 'SC_EXT_2'
| 0x0 (0x1 in Reference Design) |
Access to CPLD Registers
CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:
Some of these registers are using to show some information same as CPLD revision and boot mode while booting.
If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:
Access to CPLD Registers
CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:
i2cset -y 1 0x20 0x03 <data>
Some of these registers are using to show some information same as CPLD revision and boot mode while booting.
BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).
PUDC is the state of PUDC pin of FPGA.
CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)
BOOT_MODE shows selected boot mode.
If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:
- If boot mode via hardware is selected → Deactive(0)
- If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
- Jed file type can be one of the following types :
- (0) QSPI/SD
- (1) QSPI/JTAG
- (2) JTAG/SD
- (3) default QSPI/JTAG/SD/eMMC
- PUDC can have one of the following state:
- Pull-up activated (0)
- Pull-up deactivated (1)
- The following boot modes can displayed:
- eMMC (0)
- JTAG (1)
- QSPI (2)
- SD Card (3)
The CPLD revision, boot mode and other informations will be displayed while booting as shown:
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If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:
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title | Message while booting if CPLD firmware version is old for PCB REV04 |
Appx. A: Change History
Revision Changes
- REV02 to REV03
- changed top design from block design to text design
- added power sequencer
- added debouncing for power good signals
- added jtag_uart
- added i2c interface
- REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV03 | REV02 |
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Appx. B: Legal Notices
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